our design DRVDD is 3.3V. Does this make any difference on setup and hold time
1. Q1: In the plots provided the CLK input was not shown – only the DCO and
one data line output were shown. These signals are CMOS outputs from the ADC
and their timing does not depend on whether the input clock is sinusoidal or
2. Q2: Going to a DRVDD of 3.3V should not significantly impact the setup
and hold time values. The absolute timing (tpd and tdco) will get slightly
faster but the difference between the two delays which determine the setup and
hold times should not change significantly.