connectors, to another card (ADC is the last component in the signal chain on
the analog board before the signal goes to the FPGA on the digital board). Or
is a buffer required?
The LVDS interface is robust, and no buffer should be required, assuming that
the LVDS output traces are 100 Ohms Characteristic Impedance. For the CMOS
outputs, the load capacitance should be minimised and a buffer would probably
be required unless the trace length to the FPGS is very short.