with the AD9284-250EBZ and the HSC-ADC-EVALCZ. In the settings of the ADC
Capture Block the maximum number of samples seems to be 8388608.
The capture size is not really limited by the software so much as it is limited
by the hardware. The maximum capture size is limited by the available memory
on the data capture board. This turns out to be 64k. Depending on the
particular ADC and corresponding FPGA code, the maximum capture would be 32k
per channel for a dual, 16k per channel for a quad, etc.