pins considering that they have a 2,5V LVPECL available?
The ENCODE and ENCODE inputs are internally biased to 3.75 V (nominal), and
support either differential or single ended signals. The encode signal if DC
coupled will have to be pulled up to a common mode of 3.75Volts.
We use a Rohde and Schwartz SMG sine signal source to drive the PECL clock
circuit shown on the AD9433 evaluation board schematic for the majority of our
characterization. For high frequency characterization, we also use crystal
based sine oscillators from Wenzel Associates. As neither of these options is
practical in final applications, we recommend less expensive crystal based CMOS
clock oscillators from CTS Reeves (model MXO45-80), together with a transformer
for single ended to differential conversion. This has been shown to support
<0.25ps rms jitter. For an example of this circuit, please see the transformer
based clock circuit that is shown in the AD6645 evaluation board (see AD6645