results in a more demanding and larger PCB design and will require an FPGA with
increased pincount and LVDS receivers, that would not be the case if we use the
CMOS mode interface, so, in our application CMOS will result more cost
effective lower complexity and smaller FPGA. There is however no performance
data on the AD9446 datasheet for CMOS interfacing, only a comment saying that
CMOS mode can be used "with applications that tolerate a slight degradation in
dynamic performance". Question: how much degradation should I understand from
the words "slight degradation" This is crucial information for one to decide if
CMOS is an option or not. Could you please let me know roughly what to expect ?
It is very important issue for us at the moment
This performance is not from the chip but due to interface and it's application
as describe in the datasheet rev.0. section on "CMOS Mode*/",/* page 27 .Hence
overshoots and fast clock edge ringing etc. Since LVDS can achieve faster
clocks and virtually no ringing as the data is differential.
Bottom line is speed, board layout,routing, termination and matching play a big
factor which helps in minimise your degradation.
Also from your concern/query LVDS does not (in my opinion from past design
experienced) results in a more demanding and larger PCB design etc. in fact
performance is much better as long as you stay within routing/termination and
PCB layout rules.