Q
The datasheet states: For normal SPI operation, these pins should be tied to
AGND through a 100 kΩ resistor on each pin. These pins are both 1.8 V and 3.3 V
tolerant. However, the SDIO output logic level is dependent on the bias of the
SPIVDD pin. For 3.3 V output logic, tie SPIVDD to 3.3 V (AVDD2). For 1.8 V
output logic, tie SPIVDD to 1.8 V (AVDD1).
My question is whether the SPIVDD can be tied to 2.5V to be compatible to the
2.5V logic, since some FPGAs are 2.5V logic?
A
Yes, you can connect the SPIVDD to 2.5V to make it compatible with the 2.5V
FPGA.