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Documents AD9600: Peak detection
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  • HIGH-SPEED ADC SUPPORT COMMUNITY
  • TAGS LIST: High-Speed ADCs
  • +Absolute Group Delay: FAQ
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    • AD9600: Are the two channels synchronized?
    • AD9600: input impedance
    • AD9600: Peak detection
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AD9600: Peak detection

Question

1. Is is possible to read signal monitor values via parallel port or only
through SPI and SPORT?

2. Are power consumption figures in the datasheet specified per channel or
for the whole device? Is it possible to switch off one of the channel to save
power?

3. Peak detector values are 10-bit, but SMRC registers combined give 20-bit
value. Is it possible to read only 10 bits from those rigsetrs and get credible
result?

4. How long are signal monitor results stored in SMRC registers: until
readout or until the timer reaches 0 next time?

Answer

1. It is not possible to read the signal monitor values via the parallel
port, all the available bandwidth on this port is consumed by the output data
from the part.

2. The power consumption numbers provided in Table 1 have both channels
operating and are therefore for the entire device. Yes, one or both channels
can be disabled via the SPI port by setting bits 0 and 1 in register 0x08. The
affected channel for this write is controlled by setting the appropriate bits
in register 0x05.

3. With the power monitor in peak detect mode, only the 10 MSBs will be
valid in the signal monitor result registers.

4. The values are stored only until the next value becomes available when
the signal monitor period counter reaches zero. At that point the values are
replaced with the new values.

Tags: ad9600 5GJX0320 high-speed adcs
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