problems as follows:-
1. They are experiencing potential latch-up if both power supplies do
go on at the same time with the first one on going into current limit.
Is the device susceptible to latch up and if so are there any recommended
circuits to limit the potential for damage if this
2 The second is with respect to gain, the customer would like to achieve a
gain of 4, what would be the for the optimum value for RF. I have looked at
the table 1 on the data sheet (page 17) and are a little confused as to why
for a gain of -1 and a gain of +2 that the value for Rf and RG are shown as
being the same.
1) When applying power to the op-amp, it is reasonable to assume that, because
have big capacitors and, often, low-resistance paths to ground, supplies which
are unpowered can be assumed
to be connected to ground, or, during power-up, moving from ground towards
their final value.
So as long as the potential on all non-supply terminals is not allowed to go
outside the supply terminals then, for
most op-amps, there is no problem and THIS, rather than supply sequencing per
se is what the ctm should be concerned about.
And this is best specified WITH RESPECT TO THE AMPLIFIER TERMINALS rather than
If the i/p voltage can exceed either of the supply rails, then the i/p circuit
should be adjusted to ensure that in the event of an overvoltage condition, the
voltage to the i/p pins is kept within the max ratings.
refer to ch 7 of the practical analog design techniques seminar available at
the following page.
2)In non-inverting configuration, the gain equation = rf/rg +1, in inverting
configuration the gain equation = rf/rg, therfore the rf and rg values for a
gain of -1 = rf and rg values for a gain of +2, similar g=-2, uses similar
resistor values for g=+3.
For a gain = +4, rf/rg = 3, using a value of rf = 2K, rg =approx 665.
In selecting resistors, the values should be kept as slow as possible to reduce
the Johnson noise of the resistor, and secondly since the equivalent input
resistance on each i/p pin x input bias current results in a voltage noise
source, keeping Rg as low as possible, and selecting the value of Rs approx=
the parallel resistance of Rg and Rf. This will result in equal input
resistance seen by the bias current in each leg, which will minimize the
effects of the offset bias current.