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AD-FMCOMMS1 direct ADC access
AD6620: figure2 x axis datasheet error
AD6624A: In slave mode, can you use DR to drive SDFS input
AD6636: multiple channel Filter design
AD6640 Evaluation Board Connected To The AD6620
AD6640AST: Maximum and minimum for VREF
AD6643: How to select the modes of AD6643?
AD6644: Decoupling/grounding recommendations
AD6644: Eval Board usage
AD6644: Vref load current
AD6645: Interfacing to a FPGA
AD6645: Max input signal
AD6645: Overvoltage protection
AD6645: Selection of resistor values
AD6645: Spurious noise
AD664: thermal resistance
AD6650: Antialiasing filter
ad6654: I/Q data output pairs
AD6655: For I and Q, which one is output firstly?
AD6655: Mode 3 & 4 settings
AD6676 FAQ: Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
AD6676 FAQ: What development tools are available?
AD6676 FAQ: What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
AD6676 FAQ: Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
AD6676 FAQ: Why isn't the noise floor of the AD6676 flat?
AD6676 FAQ:I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior. Is this true and should I be concerned?
AD9027: Do you have the detail circuit of dither generator using OP27 shown in AD9042 datasheet?
AD9042: Output drive of the VREF
AD9050: full-scale output
AD9054A single ended drive
AD9057: Aperture uncertainty
AD9057: BIAS out grounding and drive current
AD9066: Random intervals
AD9066: storage temperature
AD9201: Minimum sampling frequency
AD9215: Using a DC input
AD9218 interferences at L-band
AD9218: Power supply lower than specified
AD9218: using two AD9216 - Duty Cycle Stabilizer - running the two clocks 180 degree
AD9220: clock input level
AD9220: DVDD explanation
AD9222: EVB document
AD9222: Sample Rate
AD9225: Effect of varying the clock period and duty cycle
AD9230: EVB schematic
AD9231: Differential delivery
AD9233: 0x18 register setting the input range
AD9236: About Aperture Uncertainty spec with regard to DCS
AD9238, AD9248 - Evalustion schematic Ad9238BCP-65EBZ
AD9239: header of ouput coding
AD9240: Maximum allowed power supply ripple
AD9240: SINAD specification include effect of aperture jitter
AD9244: Analog I/P impedance
AD9244: Using the VREF
AD9245_differential input configuration with AD8351
AD9246: Capacitive drive
AD9246: SNR equations, jitter calculation and Vref
AD9246: Timing parameters
AD9246: Using Opamp
AD9246: Wake up time from standby mode
AD9248: Evaluation board gereber files
AD9249: Output driver termination and drive strength
AD9254 input impedance
AD9261: ICVDD current spec typo in datasheet.
AD9262 How to solve start-up trouble
AD9265 BIST Function
AD9265 more than one part on same LVDS bus possible?
AD9268 Input understanding
AD9271 Output Varying by up to 10% from channel to channel
AD9277 in die form?
AD9280: Minimum clock frequency
AD9280: reference span
AD9283: can we connect the VD and VDD (Analog And Digital power supply) pins of AD9283 together to a single 3.3V?
AD9284 DemoBoard (UG-178) and question relevant to the max number of samples that is possible to acquire using VisualAnalog SW
AD9286 for capturing 2ns pulses
AD9288: what is the relationship between RIN and REF?
AD9410: variation of the aperture delay
AD9430: Data to DCO skew
AD9430: Grounding strategy
AD9430: Power grounds
AD9430: Unstable output
AD9432: source impedance
AD9433: Driving the encode
AD9434 startup time from standby and powerdown
AD9434: Error in datasheet CHIP_GRADE register bit settings for 500MSPS speed grade option
AD9444: Exceeding the trace length
AD9446: CMOS output
AD9460: Application using DC input
AD9461_interlacing multi ADC app-2
AD9461_SPI configuration file
AD9467 Exposed Paddle
AD9467-200: EBZ to Xilinx 1
AD9467: SPI 2.5V logic
AD9484 and HSC-ADC-EVALC
AD9600: Are the two channels synchronized?
AD9600: Peak detection
AD9613: Usage of pattern 3 and 4
AD9626: Configuration without SPI Interface
AD9627ABCPZ and AD9627BCPZ: difference
AD9640: Maximum and minimum aperture delay
AD9643: Sampling delay between ADC0 and ADC1
AD9645 Evaluation Board
AD9645 Highest Input Clock Frequency
AD9645 in a 5mm x 5mm 32-lead package
AD9645 Reduction in Power Consumption
AD9652: What is the max data rate?
AD9652: When should I use the AD9652?
AD9652: Which data capture card is used with the AD9652 evaluation board?
AD96685: Operation at high speed
AD9684 Input termination
AD9814: What is the curent status of AD9814KR?
AD9822: External reference
AD9822: O/P data in 3 channel mode
AD9822: SHA mode
AD9826: 30MSPS plot
AD9826: Are there any power supply sequencing requirements for this device?
AD9864_output signal bandwidth
AD9874: Test registers
AD9874: VCM pin external clock input
Are there considerations on utilizing the maximum power-down mode of the AD9249?
Can I directly connect Vocm of 8 ADA4932s to the Vcm output of the AD9257?
Can I take a >256K sample FFT with AD9625 using HSC-ADC-EVALEZ?
Can I use an external trigger to capture data from ADS7-V2EBZ?
Can the AD9255 LVDS outputs drive signals over longer PCB trace?
Can the AD9279-65EBZ Evalboard operate at 80MHz?
Can the AD9680 support DC coupled signals?
Can the AD9684 adjust timing between the two ADC channels?
Can the AD9684 support DC coupled signals?
Configuring the AD9826
Could AD9288 support 0.5V or 1V ref and can I use single-ended input?
DDC roadmap AD6636
Differential Input Resistance
Does the AD9245 use special techniques for reducing the KT/C?
Does the AD9249 have built-in test modes?
Does the AD9680 need a Power Sequence when turning on?
Does the AD9683 support a smaller package size
Does the AD9684 have any digital signal processing capabilities?
Frequently Asked Questions About High-Speed Data Capture Platforms
High speed ADC's control board introduction
High Speed ADCs and HSC-AD-EVALCZ
HIGH-SPEED ADC SUPPORT COMMUNITY
Highest input clock frequency supported by the AD9250
How can I analyze Squre wave with AD9236
How does the AD9625 timestamp sampled data?
How does the AD9649's input referred noise vary over the -40 to 85�C temperature range?
How is the AD9683 unique?
How is the Over-Range flag indicator set on the AD9625?
How to calculate absolute group delay
How to reduce consumption of AD9225
How to set the frequency of AD9560 PWM generator
HSC-ADC-EVALB-DC: Software and evaluation system
HSC-ADC-EVALCZ: Can I get source code for FPGA on High Speed ADC evaluation board?
I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676. Is there any trade-offs that I need to be aware of when considering this option?
Input Bandwidth and Nyquist Zone
Input clock frequency
Input Impeadance of AD9200 ( General Input Impedance of Unbuffered Switched Cap Input ADC's)
Input resistance for AD9231
Input Resistance of AD9229
Input Resistance to AD9228
Interface directly to an FPGA development kit
Interleaving two AD9481 application
Interleaving using SYNC pin
Is the AD9467's register 107h address correct?
Is the AD9684 an interleaved ADC?
Is there a solution to use the AD9272-65EBZ using the FMC interposer board?
Is there an additional data capture required in order to evaluate the AD9683?
Latency of the AD9684
LDC - state of SYNC-Pin?
ML605 Xilinx FPGA board interfacing with both AD9434 and AD9789 eval boards
Offset and Thermal Drift
Operating AD6676 at Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
RE: AD9613 Vcm max. load
Recommended ADC driver and clock distribution devices
Recommended ADC driver and clock distribution devices for the AD9645
recommended treatment for power and grounding of the AD9249 to achieve data sheet performance
Running AD9255 at lower than 10MHz sample frequency
TAGS LIST: High-Speed ADCs
the footprints and symbols of AD6657 based on Orcad.
The gerber files of AD922X evaluation board
the quick start guide for AD9212/22/52 EVB.
The schematic for AD6635 Evaluation board
What "stripes" mean in AD9266
What are the available buffer controls in the AD9680?
What are the available buffer controls in the AD9684?
What are the options for optimum clocking of the AD9249 to ensure proper operation?
What determines the AD6676’s full-scale input setting?
What is the expected AC performance of the AD9684 at high input frequencies?
What is the Full Power Bandwidth of the AD9680?
What is the power up sequence of AD6633 core and I/O?
What is the STF response of a Σ-Δ ADC and why does it matter?
What is the use for the variable input termination in AD9680? What are the options available?
What's so special about JESD204B? About Subclass 1?
When does the AD9249 require a digital reset after initial power-up?
Where can I find the BOM, layout files and the photo of AD9240 EVB, it is no longer on the product page on your website.
Why is the AD9467-FMC-250EBZ missing the on-board oscillator Y200?
We have a customer who is trying to use the AD9631 and is experiencing two
problems as follows:-
1. They are experiencing potential latch-up if both power supplies do
go on at the same time with the first one on going into current limit.
Is the device susceptible to latch up and if so are there any recommended
circuits to limit the potential for damage if this
2 The second is with respect to gain, the customer would like to achieve a
gain of 4, what would be the for the optimum value for RF. I have looked at
the table 1 on the data sheet (page 17) and are a little confused as to why
for a gain of -1 and a gain of +2 that the value for Rf and RG are shown as
being the same.
1) When applying power to the op-amp, it is reasonable to assume that, because
have big capacitors and, often, low-resistance paths to ground, supplies which
are unpowered can be assumed
to be connected to ground, or, during power-up, moving from ground towards
their final value.
So as long as the potential on all non-supply terminals is not allowed to go
outside the supply terminals then, for
most op-amps, there is no problem and THIS, rather than supply sequencing per
se is what the ctm should be concerned about.
And this is best specified WITH RESPECT TO THE AMPLIFIER TERMINALS rather than
If the i/p voltage can exceed either of the supply rails, then the i/p circuit
should be adjusted to ensure that in the event of an overvoltage condition, the
voltage to the i/p pins is kept within the max ratings.
refer to ch 7 of the practical analog design techniques seminar available at
the following page.
2)In non-inverting configuration, the gain equation = rf/rg +1, in inverting
configuration the gain equation = rf/rg, therfore the rf and rg values for a
gain of -1 = rf and rg values for a gain of +2, similar g=-2, uses similar
resistor values for g=+3.
For a gain = +4, rf/rg = 3, using a value of rf = 2K, rg =approx 665.
In selecting resistors, the values should be kept as slow as possible to reduce
the Johnson noise of the resistor, and secondly since the equivalent input
resistance on each i/p pin x input bias current results in a voltage noise
source, keeping Rg as low as possible, and selecting the value of Rs approx=
the parallel resistance of Rg and Rf. This will result in equal input
resistance seen by the bias current in each leg, which will minimize the
effects of the offset bias current.
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