AD9643: Sampling delay between ADC0 and ADC1

Q

could you please advise the sampling delay between ADC0 and ADC1 - I was not
able to find it in the datasheet

A

I have had similar questions come up in the past and the design of the AD9643
is to keep the sampling instant of the converters as close as possible. The
layout of the clock path is designed to be identical in order to keep the skew
as low as possible. This particular timing parameter is not something we have
any test data for, but based off of the layout and the expected timing from
simulations the expected variation between the two converters inside the AD9643
should be less than 10ps (including statistical variation of the devices). The
clock period is 4 ns so a variation of less than 10 ps should be pretty
negligible I’d think. I hope this information helps.