Analog.com Analog Dialogue Wiki English
Analog.com Analog Dialogue Wiki 简体中文
EngineerZone
EngineerZone
  • Site
  • User
  • Site
  • Search
  • User
EngineerZone
EngineerZone
  • Log in
  • Site
  • Search
  • Log in
  • Home
  • Blogs ⌵
    • EngineerZone Spotlight
    • The Engineering Mind
  • Browse ⌵
    • All Groups
    • All Members
  • Support ⌵
    • 3D ToF Depth Sensing
    • Amplifiers
    • Analog Microcontrollers
    • Audio
    • Clock and Timing
    • Data Converters
    • Design Tools and Calculators
    • Direct Digital Synthesis (DDS)
    • Embedded Vision Sensing
    • Energy Monitoring and Metering
    • FPGA Reference Designs
    • Industrial Ethernet
    • Interface and Isolation
    • Low Power RF Transceivers
    • MEMS Inertial Sensors
    • Motor Control Hardware Platforms
    • Optical Sensing
    • Power By Linear
    • Processors and DSP
    • Reference Circuits
    • RF and Microwave
    • Switches/Multiplexers
    • Temperature Sensors
    • Video
    • Wide Band RF Transceivers
    • Wireless Sensor Networks Reference Library
  • My EZ
  • More
  • Cancel
  • 主页
  • 浏览 ⌵
    • 收件箱
    • 个人设置
    • 会员
    • 专区列表
  • 论坛专区 ⌵
    • 放大器专区
    • 精密转换器专区
    • 音频专区
    • ADE电能计量专区
    • MEMS和传感器专区
    • 接口和隔离专区
    • Power 中文专区
    • ADUC微处理器专区
    • 锁相环专区
    • 开关和多路复用器专区
    • 温度传感器
    • 基准电压源专区
    • 资源库
    • 论坛使用指南
    • 技术支持参考库
    • 在线研讨会
    • 论坛社群活动
    • 论坛激励活动
  • More
  • Cancel
High-Speed ADCs
  • Data Converters
  • More
High-Speed ADCs
Documents AD9643: Sampling delay between ADC0 and ADC1
  • Q&A
  • Discussions
  • Documents
  • File Uploads
  • Video/Images
  • Tags
  • Managers
  • More
  • Cancel
  • New
High-Speed ADCs requires membership for participation - click to join
  • AD9695Setup_DDCon_dec16
  • 3000Mb/s lane rate
  • AD-FMCOMMS1 direct ADC access
  • AD6620 status
  • AD6620's RCF
  • AD6620: figure2 x axis datasheet error
  • AD6624A: In slave mode, can you use DR to drive SDFS input
  • AD6636: multiple channel Filter design
  • AD6640 Evaluation Board Connected To The AD6620
  • AD6640AST: Maximum and minimum for VREF
  • AD6643: How to select the modes of AD6643?
  • AD6644: Decoupling/grounding recommendations
  • AD6644: Eval Board usage
  • AD6644: Vref load current
  • AD6645: Interfacing to a FPGA
  • AD6645: Max input signal
  • AD6645: Overvoltage protection
  • AD6645: Selection of resistor values
  • AD6645: Spurious noise
  • AD664: thermal resistance
  • AD6650: Antialiasing filter
  • AD6650: Footprint
  • ad6654: I/Q data output pairs
  • AD6655: For I and Q, which one is output firstly?
  • AD6655: Mode 3 & 4 settings
  • AD6676 FAQ: Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
  • AD6676 FAQ: What development tools are available?
  • AD6676 FAQ: What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
  • AD6676 FAQ: Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
  • AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
  • AD6676 FAQ: Why isn't the noise floor of the AD6676 flat?
  • AD6676 FAQ:I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior.  Is this true and should I be concerned?
  • AD9027:  Do you have the detail circuit of dither generator using OP27 shown in AD9042 datasheet?
  • AD9042: Output drive of the VREF
  • AD9050: full-scale output
  • AD9054A single ended drive
  • AD9057: Aperture uncertainty
  • AD9057: BIAS out grounding and drive current
  • AD9066: Random intervals
  • AD9066: storage temperature
  • AD9201: Minimum sampling frequency
  • AD9211ad9230_relationship
  • AD9215: Using a DC input
  • AD9218 interferences at L-band
  • AD9218: Power supply lower than specified
  • AD9218: using two AD9216 - Duty Cycle Stabilizer - running the two clocks 180 degree
  • AD9220: clock input level
  • AD9220: DVDD explanation
  • AD9222: EVB document
  • AD9222: Sample Rate
  • AD9224
  • AD9225: Effect of varying the clock period and duty cycle
  • AD9230: EVB schematic
  • AD9231: Differential delivery
  • AD9233: 0x18 register setting the input range
  • AD9236: About Aperture Uncertainty spec with regard to DCS
  • AD9238, AD9248 - Evalustion schematic Ad9238BCP-65EBZ
  • AD9239: header of ouput coding
  • AD9240: Maximum allowed power supply ripple
  • AD9240: SINAD specification include effect of aperture jitter
  • AD9243: Grounding
  • AD9244: Analog I/P impedance
  • AD9244: Using the VREF
  • AD9245_differential input configuration with AD8351
  • AD9246: Capacitive drive
  • AD9246: SNR equations, jitter calculation and Vref
  • AD9246: Timing parameters
  • AD9246: Using Opamp
  • AD9246: Wake up time from standby mode
  • AD9248: Evaluation board gereber files
  • AD9249: Output driver termination and drive strength
  • AD9250 Evaluation
  • AD9254 input impedance
  • AD9254_output SNR-1
  • AD9261: ICVDD current spec typo in datasheet.
  • AD9262 How to solve start-up trouble
  • AD9265 BIST Function
  • AD9265 more than one part on same LVDS bus possible?
  • AD9268 Input understanding
  • AD9269 output
  • AD9271 Output Varying by up to 10% from channel to channel
  • AD9277 in die form?
  • AD9280: 40MSPs
  • AD9280: Minimum clock frequency
  • AD9280: reference span
  • AD9283: can we connect the VD and VDD (Analog And Digital power supply) pins of AD9283 together to a single 3.3V?
  • AD9284 DemoBoard (UG-178) and question relevant to the max number of samples that is possible to acquire using VisualAnalog SW
  • AD9286 for capturing 2ns pulses
  • AD9288: what is the relationship between RIN and REF?
  • AD9410: variation of the aperture delay
  • AD9430: Data to DCO skew
  • AD9430: Grounding strategy
  • AD9430: Power grounds
  • AD9430: Unstable output
  • AD9432: source impedance
  • AD9433: Driving the encode
  • AD9434 startup time from standby and powerdown
  • AD9434: Error in datasheet CHIP_GRADE register bit settings for 500MSPS speed grade option
  • AD9444: Exceeding the trace length
  • AD9446: CMOS output
  • AD9460: Application using DC input
  • AD9461_interlacing multi ADC app-2
  • AD9461_SPI configuration file
  • AD9467 Exposed Paddle
  • AD9467-200: EBZ to Xilinx 1
  • AD9467-FMC-250EBZ
  • AD9467: SPI 2.5V logic
  • AD9467_PN pattern-1
  • AD9484 and  HSC-ADC-EVALC
  • AD9600: Are the two channels synchronized?
  • AD9600: Peak detection
  • AD9613: Usage of pattern 3 and 4
  • AD9626: Configuration without SPI Interface
  • AD9627ABCPZ and AD9627BCPZ: difference
  • ad9631
  • AD9640: Maximum and minimum aperture delay
  • AD9643: Sampling delay between ADC0 and ADC1
  • AD9645 Evaluation Board
  • AD9645 Highest Input Clock Frequency
  • AD9645 in a 5mm x 5mm 32-lead package
  • AD9645 Reduction in Power Consumption
  • AD9652: What is the max data rate?
  • AD9652: When should I use the AD9652?
  • AD9652:  Which data capture card is used with the AD9652 evaluation board?
  • AD96685: Operation at high speed
  • AD9684 Input termination
  • AD9814: What is the curent status of AD9814KR?
  • AD9822: External reference
  • AD9822: O/P data in 3 channel mode
  • AD9822: SHA mode
  • AD9826: 30MSPS plot
  • AD9826: Are there any power supply sequencing requirements for this device?
  • AD9864_output signal bandwidth
  • AD9874: Test registers
  • AD9874: VCM pin external clock input
  • Are there considerations on utilizing the maximum power-down mode of the AD9249?
  • Can I directly connect Vocm of 8 ADA4932s to the Vcm output of the AD9257?
  • Can I take a >256K sample FFT with AD9625 using HSC-ADC-EVALEZ?
  • Can I use an external trigger to capture data from ADS7-V2EBZ?
  • Can the AD9255 LVDS outputs drive signals over longer PCB trace?
  • Can the AD9279-65EBZ Evalboard operate at 80MHz?
  • Can the AD9680 support DC coupled signals?
  • Can the AD9684 adjust timing between the two ADC channels?
  • Can the AD9684 support DC coupled signals?
  • Configuring the AD9826
  • Could AD9288 support 0.5V or 1V ref and can I use single-ended input?
  • DDC roadmap AD6636
  • Differential Input Resistance
  • Does the AD9245 use special techniques for reducing the KT/C?
  • Does the AD9249 have built-in test modes?
  • Does the AD9680 need a Power Sequence when turning on?
  • Does the AD9683 support a smaller package size
  • Does the AD9684 have any digital signal processing capabilities?
  • Evaluation Board
  • Evaluation Platform
  • FIFO Board
  • Frequently Asked Questions About High-Speed Data Capture Platforms
  • Gain Drift
  • High speed ADC's control board introduction
  • High Speed ADCs and HSC-AD-EVALCZ
  • HIGH-SPEED ADC SUPPORT COMMUNITY
  • Highest input clock frequency supported by the AD9250
  • How can I analyze Squre wave with AD9236
  • How does the AD9625 timestamp sampled data?
  • How does the AD9649's input referred noise vary over the -40 to 85�C temperature range?
  • How is the AD9683 unique?
  • How is the Over-Range flag indicator set on the AD9625?
  • How to calculate absolute group delay
  • How to reduce consumption of AD9225
  • How to set the frequency of AD9560 PWM generator
  • HSC-ADC-EVALB-DC: Software and evaluation system
  • HSC-ADC-EVALCZ: Can I get source code for FPGA on High Speed ADC evaluation board?
  • HSC_ADC_EVALCZ_J9 setup-1
  • HSC_ADC_EVALCZ_J9 setup-2
  • I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
  • Input Bandwidth and Nyquist Zone
  • Input clock frequency
  • Input Impeadance of AD9200 ( General Input Impedance of Unbuffered Switched Cap Input ADC's)
  • Input resistance for AD9231
  • Input Resistance of AD9229
  • Input Resistance to AD9228
  • Interface directly to an FPGA development kit
  • Interleaving two AD9481 application
  • Interleaving using SYNC pin
  • Is the AD9467's register 107h address correct?
  • Is the AD9684 an interleaved ADC?
  • Is there a solution to use the AD9272-65EBZ using the FMC interposer board?
  • Is there an additional data capture required in order to evaluate the AD9683?
  • JESD204B firmware
  • Latency of the AD9684
  • LDC - state of SYNC-Pin?
  • ML605 Xilinx FPGA board interfacing with both AD9434 and AD9789 eval boards
  • Offset and Thermal Drift
  • Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
  • RE: AD9613 Vcm max. load
  • Recommended ADC driver and clock distribution devices
  • Recommended ADC driver and clock distribution devices for the AD9645
  • recommended treatment for power and grounding of the AD9249 to achieve data sheet performance
  • Running AD9255 at lower than 10MHz sample frequency
  • TAGS LIST: High-Speed ADCs
  • the footprints and symbols of AD6657 based on Orcad.
  • The gerber files of AD922X evaluation board
  • the quick start guide for AD9212/22/52 EVB.
  • The schematic for AD6635 Evaluation board
  • Thermal Information
  • What "stripes" mean in AD9266
  • What are the available buffer controls in the AD9680?
  • What are the available buffer controls in the AD9684?
  • What are the options for optimum clocking of the AD9249 to ensure proper operation?
  • What determines the AD6676’s full-scale input setting?
  • What is the expected AC performance of the AD9684 at high input frequencies?
  • What is the Full Power Bandwidth of the AD9680?
  • What is the power up sequence of AD6633 core and I/O?
  • What is the STF response of a Σ-Δ ADC and why does it matter?
  • What is the use for the variable input termination in AD9680? What are the options available?
  • What's so special about JESD204B? About Subclass 1?
  • When does the AD9249 require a digital reset after initial power-up?
  • Where can I find the BOM, layout files and the photo of AD9240 EVB, it is no longer on the product page on your website.
  • Why is the AD9467-FMC-250EBZ missing the on-board oscillator Y200?

AD9643: Sampling delay between ADC0 and ADC1

Q 

could you please advise the sampling delay between ADC0 and ADC1 - I was not
able to find it in the datasheet

 

A 

I have had similar questions come up in the past and the design of the AD9643
is to keep the sampling instant of the converters as close as possible.  The
layout of the clock path is designed to be identical in order to keep the skew
as low as possible.  This particular timing parameter is not something we have
any test data for, but based off of the layout and the expected timing from
simulations the expected variation between the two converters inside the AD9643
should be less than 10ps (including statistical variation of the devices).  The
clock period is 4 ns so a variation of less than 10 ps should be pretty
negligible I’d think.  I hope this information helps.
  • ad9643
  • Share
  • History
  • More
  • Cancel
Comments
Anonymous
Related
 
社交网络
快速链接
  • 关于ADI
  • Partners
  • 模拟对话
  • 职业
  • 联系我们
  • 投资信息
  • 新闻中心
  • 质量和可靠性
  • 办事处与代理商
  • Analog Garage
语言
  • English
  • 简体中文
  • 日本語
  • Руccкий
电子快讯

欲获得最新ADI产品、设计工具、培训与活动的相关新闻与文章,请从我们的在线快讯中选出您感兴趣的产品类别,每月或每季度都会发送至您的收件箱。

订阅
Switch to mobile view
Analog Logo
© 1995 - 2021 Analog Devices, Inc. All Rights Reserved 沪ICP备09046653号-1
  • ©
  • 1995 - 2021 Analog Devices, Inc. All Rights Reserved
  • 沪ICP备09046653号-1
  • 网站地图
  • 隐私和保密政策
  • 隐私设置
  • 使用条款
 
Social
Quick Links
  • About ADI
  • Partners
  • Analog Dialogue
  • Careers
  • Contact us
  • Investor Relations
  • News Room
  • Quality & Reliability
  • Sales & Distribution
  • Analog Garage
Languages
  • English
  • 简体中文
  • 日本語
  • Руccкий
Newsletters

Interested in the latest news and articles about ADI products, design tools, training and events? Choose from one of our 12 newsletters that match your product area of interest, delivered monthly or quarterly to your inbox.

Sign Up
Switch to mobile view
Analog Logo
© 1995 - 2021 Analog Devices, Inc. All Rights Reserved 沪ICP备09046653号-1
  • ©
  • 1995 - 2021 Analog Devices, Inc. All Rights Reserved
  • 沪ICP备09046653号-1
  • Sitemap
  • Privacy & Security
  • Privacy Settings
  • Terms of use
EngineerZone Uses cookies to ensure you get the best experience in our community. For more information on cookies, please read our Privacy & Security Statement.