How is the AD9645 residing in a small 5mm x 5mm 32-lead package?
The AD9645 family output data interface consists of 2 serial LVDS lanes per ADC
channel. This reduces the number of traces required to the receiving FPGA (or
asic). A data output clock and frame output clock are provided for the FPGA to
reassemble the serial data. The LVDS serial data rate is as high as 500 Mbps,