means 3000 Mb/s lane rate if I use 4 lanes.
Is it possible to do so or must I use 2 lanes and 6000 Mb/s?
I want to use the lower 3000 Mb/s speed to reduce the risk in the design.
In order to reduce the risk,you can take many steps
- Run simulations using IBIS-AMI models for the ADC JESD204B Tx etc.
- Use pre-emphasis and swing controls on the ADC JESD204B Tx
- Use receive equalization on the Xilinx Rx
It would be impossible for us to guarantee link performance at 3Gbps/lane
across all voltages and temperature. This is why we have limited the low end of
the PLL to 6.25GHz. The ADC will work at 3Gbps at room temp, but this has only
tried on a handful of parts. We do not have a statistical lot data. The
design team advises against using it. Hence the recommendation to use