Yes. The AD9684 has flexible timing delay adjustments. The input clock divider
AD9684 provides phase delay in increments of ½ the input clock cycle. A fine
delay feature allows further sampling edge adjustment per channel. This fine
delay can be adjusted from -151.7ps to +150ps in 1.7ps increments. This is
useful in reducing the quadrature errors introduced in a direct conversion
(I/Q) receive architecture.