pin of about 1.7V. This bias is derived from a potential divider, with a 4K7
resistor and a 2K5 resistor. We’re only using two channels of the 9822, the
‘B’ channel input is grounded. The problem we’re seeing is that the 9822 seems
to load the offset input fairly heavily, dependant on the values seen on the
inputs - this manifests itself as crosstalk between the inputs. Varying a DC
input on one channel moves the other channel around. Questions:
1. Is this expected behaviour? 2. How does the AD9822 avoid this when using
CDS mode? - The internal schematic on page 12 of the datasheet suggests that
there would be a similar problem (loading across the 5k internal ‘resistor’)
3. Would you suggest that we buffered the offset voltage before presenting it
to the AD9822 - clearly this pin will draw quite significant amounts of current
from the buffer - will this be OK?
In SHA mode the OFFSET pin is sampled so you have all the problems of driving a
switched capacitor input (requires low source impedance and high current
drive). The offset pin is a switched-cap input just like the figure 10 shows in
SHA mode. It is possible to get away with a using low value resistor divider
for very low end, low cost consumer applications. Usually, this pin is
grounded. But, for best results, the offset pin should be a low source
impedance, so buffering the resistor divider is the way to go.
There is no crosstalk issue in CCD mode ( less than 1 lsb ) because individual
5K resistors are used for each channel, and the sampling switches are not
clocked the same as SHA mode.