Interfacing LTC2386 with Spartan 6 for operatig at  7.5 to 10 MSPS


I am working on LTC 2386 for application based on Spartan 6. I referred source code for it, which was for the Altera CPLD. I have been trying to port the code in XIlinx using XIlinx alternative to the prescribed blocks like PLL and DDRIO.

I am getting good data till 5 MSPS sampling rate, with sampling clock DCO of 40 MHz.

But when I am using it for higher frequencies, i.e Sampling rate 7.5 MSPS with DCO 150 MHz usign IDDR2 block, I am not getting expected data.

I tried the code with Test Pattern in two lane mode and Test pattern is receiving correctly.

I have posted oscilloscope image for data after IDDR2 block. This shows one channel data, dco and Q0A and Q0B the output of IDDR2 block.I am geting test pattern data as CC3F.

I would appreciate it, if you could provide me sample code for xilinx, or help me out with the issue.


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