Hello,
I have a question about SCK timing for exiting NAP mode. According to the datasheet, we should send a pulse on SCK showing Fig.8 on the datasheet.
Can I exiting NAP mode if I send the pulse like a following timing?
Best regards,
Akira
LTC2312-12
Production
The LTC2312-12 is a 12-bit, 500ksps, serial sampling A/D converter that draws only 3mA from a single 3V or 5V supply. The LTC2312-12 contains an integrated...
Datasheet
LTC2312-12 on Analog.com
Hello,
I have a question about SCK timing for exiting NAP mode. According to the datasheet, we should send a pulse on SCK showing Fig.8 on the datasheet.
Can I exiting NAP mode if I send the pulse like a following timing?
Best regards,
Akira
If the LTC2312 is already in NAP mode before the first CONV pulse shown, the rising edge of SCK will wake the part and the second CONV pulse will start a conversion. The time between the rising edge of SCK and the rising edge of CONV should be at least 50ns to satisfy the twake_nap time of the data sheet.
Hi,
I think you are asking if an SCK pulse in between the first and second CONV pulses will prevent the ADC from going into NAP mode. The answer to that question is yes.