AD8285 Application problem

Hello! 

When using the AD8285 for the first time, I would like to ask questions about CLK+, CLK-. I created two routes through the AD9515BCPZ (clk is 40mHz). 

Output Phase offset = 0;

OUT0 Can Be Divided by 16; 

OUT0: LVPECL

OUT1: LVDS 

Out0 is provided to AD8285. I want to ask if the generated 40m÷16=2.5m is satisfied. Or are there other ways? Thank you 

Also ask about the role of AUX, MUXA, and DSYNC. I do not really get it.

第一次使用AD8285,想问CLK+,CLK-的问题。我是通过AD9515BCPZ(clk为40mHz)产生两路,

Output Phase offset = 0;
OUT0 Can Be Divided by 16;

OUT0: LVPECL
OUT1: LVDS

out0 提供给AD8285。想问产生的40m÷16=2.5m,是否满足使用。还是有其它方法?谢谢

另外询问一下AUX,MUXA,以及DSYNC的作用。我不是很明白。

  • 0
    •  Analog Employees 
    on Apr 22, 2021 10:10 AM

    Hi,

    The minimum clock rate is 10MSPS, so clock should be at least 10MHz as well.

    AUX - a logic high forces to directly switch or be able to input directly to Channel ADC INADC+/INADC-

    MUXA - Logic high forces to Channel A unless AUX is asserted

    DSYNC - indicates when Channel A data is at the ADC output and when data for each active channel follows sequentially with each clock cycle

    Below is sample relationship between DSYNC and MUX A for example.

    DSYNC is  always aligned to Channel A when multiple channels are activated as described in Figure 26 of the datasheet.

    When MUXA is triggered, it means Channel A is selected and DSYNC is deactivated.

    The image shows one of the events where MUXA is triggered and after around 163ns or 3 cycles of DSYNC, the DSYNC stays at channel A.

    This part of the datasheet also describes the role of AUX, MUXA and DSYNC.