Post Go back to editing

AD9208-3000EBZ Multichip Synchronization

Hi everyone,

I am having problems with AD9208 multichip synchronization. I have two AD9208-3000EBZ boards. Each of them is separately connected to its own VCU118 FPGA board via FMC+.

I  operate the JESD20b links in subclass 1. The  two AD9208-VCU118 links shares the same 3GHZ sampling clock sources  and the same GTY reference clock source . The common sysref signal are generated from one of those VCU118s. The sysref was found to meet the setup/hold time requirement of the AD9208 via reading the  sysref status register 0x0128.

Figure 122 on page 81 of the  AD9208  specification (attached along with this post) describes the flow chart of the sysref capture. I operated the syref capture in Normal mode,  I am  actually confused with how this flow chart is actually used by the AD9208.

Below are my questions:

1. Is the flow chart in Figure 122 used after the initialization procedure on page 72 (which use Table 32) is finished?

2. Does the AD9208 keeps operating the flowchart in the Figure 122 during its operation?

3. My initialization sequence  is as followings:

  - Step 1: Initialize the link as described on page 72 and  Table 32.

  - Step 2:  The FPGA generates the comon sysref  to  all AD9208 and JESD Rx.

  - Step 3:  The two FPGAs then assert the sync~ signals.

Is there anything wrong with my sequence?

4. Using the above steps, the result is that I can see the ADC samples being captured very well by each board . Within each  board, the data samples are  aligned between its two ADC channels.

Unfortunately, when I compared the data between the two boards , they were  not aligned even if I used the ramp pattern genartors or I used  the external input source,  I am sure that the data that I compared were captured at the sametime on the two boards. More importantly, when I re-initialized the link by repeating the above steps, the amount of data misalignment varied.

I am wondering if I am missing somethinng?

5. Does the ramp pattern generator of the ADC test mode are reset everytime we re-initialized the  JESD link?