AD9864 CLK INPUT

Hi Abidin,

Possibly to be assumed, but have you consulted the AD9864 datasheet? Lots of good information there.

http://www.analog.com/media/en/technical-documentation/data-sheets/AD9864.pdf

Best Regards,

Arik

Hi Arik,

Yes, i have consulted the AD9864 data sheet.

But, there isn't detailed information in it.

We designed our PCBs according to EVB schematic which shows AC coupled driving.

Thanks.

Abidin

Hi Arik,

Below message is received from Tony Ha and it clarifies the stuation.

 ***************************************************************************************************************************

• They ask  when they use external clock (24 MHz,CMOS output VCTXO) should this external clock to be connected CKLP input as AC coupled ?
  Yes……………Best to AC couple with 0.01 uF to CLKP input with CLKN connected to 0.01 uF to AGND.

• Is max external clock frequency 26 Mhz ?
  YES
• Do they need to apply reference signal to FREP input even they don’t enable clock synthesizer ? -  They have connected it to the GRND on their design.
  This is OK. 
  Also……………make sure that SYNCB is tied to VDDH if not used!

**************************************************************************************************************************** 

Best regards,

Abidin

Hi Abidin,

So what specific concerns did you have with the clock input? In terms of driving and external clock (and Tony Ha had answer some of these questions), you would need to AC-couple the inputs unless 1.6V common-mode isn't and issue. 26MHz max.

The inputs are referenced to VDDC, so your input swing cannot be higher than this. The absolute max ratings for these pins tell you when damage to the part will occur.

You need to disable the internal LC tank circuitry to drive the clock externally.

Best Regards,

Arik

Hi Arik,

We solved the problem.

We recognized that It was related with ADC settings.

Thank you very much for you support.

Best regards,

Abidin