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AD-FMCDAQ2-EBZ: P/N polarity swap on Channel B for both AD9680 inputs and AD9144 outputs. Intentional, and is it documented?

Thread Summary

The user observed a deliberate differential polarity swap on Channel B for both the AD9680 (ADC) and AD9144 (DAC) in the AD-FMCDAQ2-EBZ. The swap is intentional to simplify PCB routing and is not automatically compensated in HDL or software. For the AD9680, the Sample Invert feature (Register 0x561, Bit[2]) can correct the polarity after selecting the channel (Register 0x008).
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Category: Datasheet/Specs
Product Number: ad-fmcdaq2-ebz

Hi,

I'm working with the AD-FMCDAQ2-EBZ and noticed what looks like a deliberate differential polarity swap on Channel B for both the AD9680 (ADC) and the AD9144 (DAC). I'd like to confirm the intent and whether it's documented anywhere.

1) AD9680 analog inputs
The Channel A and Channel B front-ends (T101/T100 vs. T103/T102, ETC1-1-13 double balun) are topologically identical, but the net labels at the AD9680 are swapped:
- Channel A: top leg (T101 pin 3) = VINA_P, bottom leg = VINA_N
- Channel B: top leg (T103 pin 3) = VINB_N, bottom leg = VINB_P
So for the same signal at IN_A and IN_B, I expect the Channel B digital output to be inverted (180°) relative to Channel A.

2) AD9144 DAC outputs
Same pattern on the DAC side (T3/T12 vs. T4/T13, ADTL1-12+ / ADT2-1T+):
- Channel A: OUT0_P to T3 pin 1, OUT0_N to T3 pin 3
- Channel B: OUT1_N to T4 pin 1, OUT1_P to T4 pin 3
So identical digital samples on DAC0 and DAC1 should produce inverted analog signals at OUT_A vs. OUT_B.

Questions:
1. Is this swap intentional (I assume for routing, given the mirrored OUT0/OUT1 pin order on the AD9144 package)?
2. Is it documented in the AD-FMCDAQ2-EBZ user guide, wiki, or reference design? I couldn't find it.
3. Do the ADI HDL (daq2 project) or the no-OS / Linux drivers compensate for it (e.g. sample negation or a polarity register), or is the user expected to handle it?
4. Do the AD9680 or AD9144 have a per-channel invert setting you'd recommend for correcting it?

This matters for coherent multi-channel work (I/Q, phase alignment, DAC-to-ADC loopback testing). In loopback, A-to-A and B-to-B would come back with the same sign, but A-to-B or B-to-A would be negated, so I'd like to confirm before correcting it in my design.

Thanks!

Parents
  • Hi  

    The polarity swap on Channel B is intentional and was primarily done to simplify PCB routing. As a result, Channel B is inverted relative to Channel A on both the AD9680 input path and the AD9144 output path.

    This inversion is typically not compensated automatically in the HDL or software and should be taken into account when performing coherent measurements, phase comparisons, or loopback testing.

    For the AD9680, polarity can be corrected in the digital domain using the Sample Invert feature (Register 0x561, Bit[2]). Be sure to first select the appropriate channel using Register 0x008 (Channel Select) before applying the inversion.

  • Thanks for your response! I just hope you could add a note to any part of the AD-FMCDAQ2-EBZ's System Level Documentation to mention this inversion. Just to give a heads up to future users, as it took me some time to spot that the inversion is in the PCB and not in the AD9680 or the AD9144 digital path.

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  • Thanks for your response! I just hope you could add a note to any part of the AD-FMCDAQ2-EBZ's System Level Documentation to mention this inversion. Just to give a heads up to future users, as it took me some time to spot that the inversion is in the PCB and not in the AD9680 or the AD9144 digital path.

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