Common Mode Voltage & ADC input Voltage

Hi Ninja22, 

Thank you for using AD9257. We are looking into your query and will get back to you as soon as possible. 

Hello ADI Team,

I am designing a system using the AD9257-65 (14-bit, 8-channel, 65 MSPS) with a high-speed fully differential amplifier (FDA) as the ADC driver.

My present operating condition is:

• ADC sampling rate: 30 MSPS
• Analog input: approximately 10 MHz square/pseudo-analog waveform
• ADC differential input: up to 2 Vp-p
• ADC output: 8 serial LVDS channels
• ADC and FPGA are located on separate PCBs and connected through a harness.

I would appreciate clarification on the following points.

1. ADC input capacitance and SPICE modelling

The datasheet specifies:

• Differential input resistance: 5.2 kΩ
• Differential input capacitance: 3.5 pF
• Switched-capacitor input architecture

However, I cannot find the actual internal sample-and-hold capacitor, switch resistance, sampling capacitor parasitics, or equivalent input RC values.

For an accurate SPICE simulation of the FDA → AD9257 interface:

1. Is the 3.5 pF differential input capacitance the appropriate value to use for an external SPICE model?
2. Can ADI provide the recommended equivalent input model, including:
   • sampling capacitor
   • switch resistance
   • input parasitic capacitance
   • differential/common-mode parasitics?
3. If the internal capacitor values are proprietary/not available, what simplified input model should be used for designing the external RC network?

I would prefer not to assume an arbitrary internal sampling capacitor because the external filter and FDA settling performance depend strongly on the switched-capacitor input.

2. External RC filter after the FDA

The AD9257 datasheet recommends a differential RC network to isolate the FDA from ADC kickback and limit unwanted broadband noise.

For my 10 MHz signal and 30 MSPS sampling rate, what would ADI recommend as a starting point for:

• Series resistor on VIN+
• Series resistor on VIN−
• Differential capacitor across VIN+ and VIN−
• Optional common-mode capacitors

For example, is a network such as 33 Ω + 33 Ω series resistors with approximately 5–6 pF differential capacitance a reasonable starting point, followed by simulation/tuning on the actual PCB?

I would also like to understand the recommended procedure for selecting these values considering the specified 3.5 pF ADC differential input capacitance.

3. 10 MHz square wave and FFT/ENOB/SNR/SFDR

My actual signal is a 10 MHz square/pseudo-analog waveform, rather than a pure sine wave.

For determining the standard ADC dynamic-performance parameters:

• SNR
• SINAD
• ENOB
• SFDR

should I perform the standard measurement using a low-distortion sinusoidal input, as used in the AD9257 datasheet, and separately evaluate the ADC response to my actual square/pseudo-analog waveform?

At 30 MSPS, a 10 MHz square wave also contains harmonics above the Nyquist frequency. Therefore, I understand that the square-wave FFT would characterize the complete system response to the actual waveform rather than provide the standard ADC ENOB/SNR/SFDR measurement.

Please confirm the recommended test methodology.

4. Sampling rate and LVDS data rate

At a 30 MSPS sample rate, each ADC channel produces:

14 bits/sample × 30 MSPS = 420 Mbps per serial LVDS channel

Since the AD9257 has eight ADC channels, this corresponds to:

8 × 420 Mbps = 3.36 Gbps aggregate serial data

The datasheet states that each ADC channel has a separate serial LVDS stream and uses DDR transmission.

Therefore, is the correct FPGA interface implementation:

• 8 LVDS data pairs
• 1 DCO differential pair
• 1 FCO differential pair
• 420 Mbps serial data rate per ADC channel at 30 MSPS

with the FPGA capturing data using the source-synchronous DCO?

5. LVDS buffer between ADC and FPGA

The ADC and FPGA are on separate PCBs connected through a harness.

The AD9257 datasheet recommends a point-to-point LVDS connection with a 100 Ω termination at the receiver and states that trace length and routing affect timing performance.

In this application, is an additional LVDS buffer/re-driver actually required between the AD9257 and FPGA, or should the ADC LVDS outputs directly drive the FPGA LVDS inputs with:

• controlled-impedance differential harness
• 100 Ω differential termination at the FPGA
• matched differential pairs
• appropriate length/skew control?

If a buffer is recommended for a longer harness, could you provide guidance on the maximum practical cable/harness length or the criteria for determining when an LVDS buffer becomes necessary?

I would also appreciate any ADI application note, reference design, evaluation-board schematic, or other literature supporting the recommended ADC-to-FPGA LVDS interface.

Thank you.

Hi Ninja22, 

1. The analog inputs of the AD9257 are not internally dc-biased. An external circuit establishes the common-mode voltage at VIN+ and VIN-. The device provides an internally generated common-mode reference at the VCM pin, which may be used to bias the input network or supply it to the VOCM pin of a compatible FDA. For optimum performance, the datasheet recommends:

The device can operate over a wider common-mode range, as shown in Figure 44, but 0.9 V is the recommended operating point. (Note: You cannot program the output of the VCM pin of the AD9257)

The AD9257 VCM pin can be used to set the common-mode voltage of an FDA. Provided that the FDAs input common-mode range is within the VCM pin output voltage (VCM = 0.9V). (Note: VCM pin has maximum current load of about 1mA to 1.5mA)

2. A measured VCM of 0.864 is reasonably close to the recommended 0.9V common-mode voltage. Figure 44 shows the ADC functioning over a wider common-mode range. The data sheet does not specify VCM-output tolerance but rather an operating point. For calculations, use the actual measured common mode to determine the instantaneous measured pin voltages.

3.For a 2 V p-p analog input:

For a balanced differential signal:

A 2 V p-p differential signal has:

Therefore, each individual line has:

With Vcm = 0.9V:

Thus, both inputs swing between 0.4V and 1.4V:

Differential Output: 

4. The voltage on VIN+ and VIN− should remain within −0.3 V to 2.0 V, as specified by the datasheet absolute maximum ratings. Exceeding these limits may result in degraded operation or potential damage to the ADC. The 2 V p-p differential input range is defined by the ADC reference voltage (VREF = 1 V). The reference voltage sets the ADC's full-scale differential input range; therefore, both the individual input voltages and the differential input voltage must remain within their respective limits.

If your FDA produces VIN+ = -0.4 V and VIN− = +0.6 V, the differential voltage is -1.0 V, which is within the ADC's full-scale differential range. However, VIN+ exceeds the absolute maximum rating because it is below -0.3 V. Therefore, this condition is outside the valid operating range of the ADC and could potentially damage the ADC if it is sustained for extended periods.

To ensure proper operation, each input pin (VIN+ and VIN−) should remain within the specified input voltage range of -0.3 V to 2.0 V. In addition, the differential input voltage should remain within the ADC's full-scale input range of 2 V p-p when VREF = 1 V.

5. For the stated instantaneous voltages: Vin + = -0.6V and Vin - = 1.4V

This is not a valid negative full-scale condition for a 2 V p-p differential ADC range. The valid differential range is -1V to 1V (2Vpp).

A differential value of −2.0 V is beyond negative full scale and will produce an overrange or clipped output code. In addition, VIN+ = −0.6 V violates the −0.3 V absolute maximum rating.

In addition, VIN+ = -0.6 V exceeds the absolute maximum rating of the VIN+ pin. This condition may cause the waveform to be clipped and could potentially degrade the performance of the ADC if sustained for an extended period of time. To ensure proper operation, both VIN+ and VIN− should remain within the specified input voltage range of -0.3 V to 2.0 V. Operating either input outside this range may result in clipping and could potentially degrade the performance of the ADC.

6.Configure the FDA output common-mode voltage to approximately 0.9 V, preferably using the AD9257 VCM output if it is compatible with the FDA VOCM input and does not excessively load the VCM pin. Decouple the ADC VCM pin to ground with 0.1 µF.

For a full-scale 2 V p-p differential signal, configure each FDA output to swing 1 V p-p, or ±0.5 V peak, around 0.9 V. VIN+ and VIN− must be equal in amplitude and 180° out of phase. Each ADC input therefore swings from approximately 0.4 V to 1.4 V

7. The input voltage applied should be within the absolute maximum ratings of the device and should not be operated at or beyond its recommended value. The datasheet recommends VCM = 0.9V for optimal performance.

8. By default, the AD9257 digital output is set in two’s complement this can be set by configuring the appropriate register. You may refer to this app note for further discussion about digital outputs: MT-009: Data Converter Codes-Can You Decode Them?

10. For detailed discussion for measuring the actual ADC performance you may refer to these application notes:

1. AN-835: Understanding High Speed ADC Testing and Evaluation | Analog Devices,
2. MT-003:Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor
3. Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1 | Analog Devices
4. Dynamic Testing of High-Speed ADCs, Part 2 | Analog Devices
5. MT-010: The Importance of Data Converter Static Specifications-Don't Lose Sight of the Basics! 

11. You may refer to my answer in bullet number 3 for VIN and VCM.

I attached some reference app notes that might be useful to you:

MT-075: Differential Drivers for High Speed ADCs Overview (analog.com)
AN-1026: High Speed Differential ADC Driver Design Considerations | Analog Devices
AN-0990: Terminating a Differential Amplifier in Single-Ended Input Applications | Analog Devices
AN-2539: Single-Supply, DC-Coupled 16-Bit, 125 MSPS Analog Front End for Bipolar Input Signals | Analog Devices

Hello,

Could you please provide the internal architecture details of this pipeline ADC, particularly the relevant internal capacitance values and sampling/hold capacitor information?

I am currently designing the input filter and would like to accurately determine the required C_SH (sample-and-hold capacitance), acquisition time, and appropriate filter cutoff frequency for stable and optimized ADC operation.

If available, could you please provide the following information:

1. Internal sample-and-hold/sampling capacitor (C_SH) value or its equivalent input capacitance.
2. Any relevant internal switching capacitance or capacitor network associated with the ADC input.
3. Acquisition time and settling requirements of the input sampling network.
4. Recommended source impedance and input RC filter configuration for the ADC.
5. If available, an SPICE model or behavioral model that includes the relevant input sampling characteristics and internal capacitances.

The objective is to model the ADC input network in SPICE and determine the appropriate RC filter values and cutoff frequency while ensuring adequate settling and smooth operation at my intended sampling and input signal frequencies.

 an equivalent input model or recommended simulation model that represents the ADC's sampling behavior would also be very helpful.

Thank you 

How can I best utilize VisualAnalog for my custom ADC design, considering that there is no corresponding evaluation board available? Please suggest what parameters or aspects of the ADC signal chain I can simulate in VisualAnalog and what useful analysis/results I can extract from it for optimizing and validating my design.

Hi Ninja22, 

The AD9257 uses a unbuffered input architecture, as such, to model its analog input you should use its S-parameter model that can be found in the product page. For reference: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs Application Note (AN-827)

Hi Ninja1 

Please see my response below:

1. The AD9257 uses a unbuffered input architecture, as such, to model its analog input you should use its S-parameter model that can be found in the product page. For reference: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs Application Note (AN-827). 
   
   
2. For a starting point, I recommend reviewing the AD9253 evaluation board schematic, since the AD9253 and AD9257 belong to the same ADC family. The RC network used between the FDA and the ADC inputs can serve as a useful reference design. You may also want to check out the ADA4930 as it's one of the FDA used together with the AD9253.
   
   For a 10MHz input signal, a practical starting point would be to place the filter cutoff frequency somewhat above the frequency of interest (e.g., 15MHz to 20MHz) to maintain a flat passband while still providing attenuation of broadband noise.

3. For standard AC performance measurements, you may use AN-835 to verify that the ADC is operating within its specified performance limits. A separate evaluation using the actual application signal is also recommended, as it will provide a more representative assessment of the applicate specific performance.
   
   
4. Your understanding for this is correct. You may also check the AD9257 schematic so that you can use its EVB-to-FPGA connections as a reference for your design.
   
   
5. An additional LVDS buffer is not required if the datasheet recommendations are followed when routing the differential signals between the ADC and FPGA. This can be achieved by using controlled-impedance differential pairs, 100 Ohm differential termination, ensuring that the differential traces are routed close together and are length matched, and the trace length to be less than 24 inches. 

Relevant Application Notes: 
Understanding and Designing Differential Filters for Communications Systems | Analog Devices
A Practical Guide to High-Speed Printed-Circuit-Board Layout | Analog Devices
"Rules of the Road" for High-Speed Differential ADC Drivers | Analog Devices
A Short Course in PCB Layout for High-Speed ADCs | Analog Devices

Hi Ninja22, 

You may use VisualAnalog to estimate the expected ADC performance under different operating conditions. For example, you can evaluate the effects of clock jitter on performance of the ADC and observe the expected output in both time and frequency domains for a given input signal. This allows you to analyze metrics such as SNR, SFDR, SINAD, Harmonic distortions, and noise floor to help optimize and validate your design. 

See App Note for detailed discussion: AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual | Analog Devices