Category: Hardware
Product Number: AD9254S
We are seeing odd startup behavior on several AD9254 devices and would like guidance on the correct way to reset and initialize the ADC.
System overview
- Multiple AD9254s interface to an FPGA.
- The FPGA generates the ADC sample clock (CLK±).
- A power‑on reset (POR) circuit holds the FPGA in reset until all power supplies are stable.
- After POR releases the FPGA, the FPGA runs its initialization sequence and then starts driving the ADC sample clock.
- We do not use the SPI port; the ADCs run in their default pin‑mode configuration.
Issue description
With other ADCs we usually perform a hard reset using a dedicated reset pin. The AD9254 does not have a reset pin, so we are relying on power‑up behavior. The PDWN/OEB pins are not connected to the FPGA.
On our boards, at startup we observe:
- The DCO clock is not stable for some time after the FPGA starts the sample clock.
- The Out‑of‑Range (OR) flag is asserted during this time.
- The ADC data is clearly incorrect (not consistent with the analog input).
- We have multiple AD9254 devices on the same board, and each device takes a different amount of time before the DCO, OR, and data become normal and stable.
- Once the devices settle, the data looks correct and performance is as expected.
Questions
- What is the recommended reset / initialization sequence for the AD9254 at power‑up?
- Is it expected that DCO and OR may be unstable for some period after power‑up or clock start, and if so, what maximum settling time should we design for before trusting the data?
Thank you in advance!
