Category: Software
Product Number: HSC-ADC-EVALCZ
I am using an AD9266-80EBZ with an HSC-ADC-EVALCZ capture board. VisualAnalog programs the board with AD9266_Main.bin. I would like to modify the FPGA design to implement digital downconversion and decimation directly in the Virtex-4.
Could you provide the complete, buildable FPGA source project corresponding to AD9266_Main.bin, including:
- Xilinx ISE project files
- Verilog/VHDL source
- UCF constraints
- required IP/core files
- build/programming instructions
The installed FPGA image targets an XC4VFX20 device. I would like to first reproduce the stock build unchanged, then make DSP modifications.
