KCC's Quizzes AQQ305 about a mutual exponentiation equation
1. Quote of the month: "A train station is where a train stops. A bus station is where a bus stops. I have a work station on my desk, so..." - unknown
2. Quiz AQQ305 about finding a mutual exponential equation
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September Monthly Blog Quiz! Read the blog, take the quiz, and you could win a gift card
Quiz: How Well Do You Know Adaptive Power Switching?
Is your I/O module overheating? The AD74416H's Adaptive Power Switching (APS) can cut heat dissipation by up to 40% — but how well do you really understand how it works?
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LTC2274
Production
The LTC2274 is a 105Msps, 16-bit A/D converter with a high speed serial interface. It is designed for digitizing high frequency, wide dynamic range signals...
Datasheet
LTC2274 on Analog.com
Hi,
I am planning to Provide SYNC to LTC2274 from my FPGA LVDS interface in a DC Coupled manner.
In LTC2274 , SYNC has 1.6V VSICM Internally Set. How to disable internal biasing?
My FPGA has VOCM of 1.1V with 0.4V swing. this 1.6V bias will damage my FPGA pins.
Kindly suggest how to connect.
Thanks in-advance,
Deva
Hi Deva1998
Thanks for using LTC2274.
The LTC2274 SYNC input has an internal common-mode bias of approximately 1.6 V (V_SICM), and there is no documented provision for disabling this bias.
Given that the FPGA LVDS output operates with a 1.1 V common-mode voltage and a 400 mV differential swing, a direct DC-coupled connection is generally not recommended due to the potential common-mode mismatch.
The recommended solution is to AC-couple the differential SYNC signals and allow the LTC2274 to establish its own common-mode voltage through its internal bias network. This approach helps avoid common-mode conflicts and minimizes any potential interaction between the LTC2274 bias circuitry and the FPGA LVDS outputs.
To provide a more specific recommendation, could you please share the FPGA family or device being used? This will allow us to review the LVDS I/O specifications and suggest an appropriate interface scheme.
Hi Jalipio,
Thanks for getting back.
AC-coupling the differential SYNC signals, is it Suitable for pulsed sync signals? DC coupling is usually recommended right?
I am interfacing with Agilex 7 FPGA, which has below specification,
Kindly suggest an appropriate interface scheme.
Thanks in-advance,
Deva
Hi Deva1998
Upon closer review of the LTC2274 datasheet, the SYNC input specification includes an "externally set" common-mode range of 1.1 V to 2.2 V. This suggests that the SYNC inputs may be driven by an external differential source that establishes its own common-mode voltage, provided it remains within the specified range. Since the Agilex 7 LVDS output common-mode voltage is approximately 1.1 V, it appears to be within the specified SYNC common-mode input range.
