| SLA Status | Assignee | Support Status |
|---|---|---|
| SLA Closed. Met after 44 hours |
JAlipio |
Awaiting Company Response |
AD9680
Recommended for New Designs
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold...
Datasheet
AD9680 on Analog.com


Hi ad9680
Based on your setup, the configuration appears to be L, M, F = 2, 2, 2; N' = 16; Decimation = 1 (full bandwidth) — please confirm if this is correct.
The issue is not primarily due to the trace length mismatch between the ADC and FPGA; it is more likely driven by clock quality degradation. It is important to ensure that a clean, low-jitter clock is delivered to both devices, and that the differential clock pairs to the ADC and FPGA are well matched in terms of length, impedance, and routing to preserve signal integrity.
Additionally, take into account the PLL lock time (~2 ms) when evaluating link stability.
