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Periodic Link Loss in AD9680 Data Acquisition

Category: Software
Product Number: AD9680
I am currently using an FPGA to implement data acquisition with JESD204B Subclass 1 and the AD9680 ADC. The FPGA model is Xilinx Zynq-7035. When operating in Subclass 1 mode, periodic link loss occurs during tests at different data rates.
For instance:
  • With an input clock of 312.5 MHz (sourced and synchronized for both FPGA and ADC), lane count L=2, and a line rate of 6.25 Gbps;
  • And with an input clock of 500 MHz and a line rate of 10 Gbps.
In both cases, the link drops after approximately 0.5 ms. Via Vivado debugging, we confirmed the GT_PLL_LOCK signal is lost. The GT_PLL_LOCK signal recovers automatically after around 113 core clock cycles.
We also conducted tests in JESD204B Subclass 0 mode. After the SYNC signal is asserted, the data link breaks shortly after acquisition starts, which rules out issues related to the SYSREF signal.
We noticed a mismatch in the trace lengths of the clock lines feeding the ADC and FPGA on the PCB. The external clock first connects to the ADC, then travels an additional 10 centimeters before reaching the FPGA’s clock pin.
Could this link loss be caused by the inconsistent clock trace lengths in the PCB design? If yes, please explain the underlying principle. Are there any other potential root causes? Your professional advice would be greatly appreciated

  • Hi  

    Thank you for using AD9680.

    Kindly give time to the product owner ( ) to look into this and provide their response.

    Thanks,

    Kim

  • Hi  

    Based on your setup, the configuration appears to be L, M, F = 2, 2, 2; N' = 16; Decimation = 1 (full bandwidth) — please confirm if this is correct.

    The issue is not primarily due to the trace length mismatch between the ADC and FPGA; it is more likely driven by clock quality degradation. It is important to ensure that a clean, low-jitter clock is delivered to both devices, and that the differential clock pairs to the ADC and FPGA are well matched in terms of length, impedance, and routing to preserve signal integrity.

    Additionally, take into account the PLL lock time (~2 ms) when evaluating link stability.

  • Thank you very much for your reply. My configuration is correct: L, M, F = 2, 2, 2, N' = 16, and the decimation factor is set to 1 (full bandwidth mode).
    The clock signal is generated by an SMB100A signal source. I have also attached the schematic of the clock circuit for your reference. Please check if there are any flaws in the design.
    Within a duration of 0.5 ms: at a 312.5 MHz clock and 6.25 Gbps data rate, approximately 153,600 samples can be captured; at a 500 MHz clock and 10 Gbps data rate, around 248,960 samples can be acquired. The sine wave display and performance metrics all work properly during this period.
    As you mentioned earlier, length, impedance and routing matching are critical for differential clock pairs. We have implemented 100 Ω impedance matching for all clock lines, GT clocks and data lines. In addition, length matching has been applied to GT clock and data lines.
    The only notable discrepancy is a 10 cm length difference between the differential clock traces feeding the ADC and FPGA; all other parameters are nearly identical. Could you please help us further analyze this issue?

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