AD9689 JESD PLL Lock Issue at 1 GSPS

Hi Team,

I am bringing up the AD9689 in Full Bandwidth Mode using RTL code based on the initialization sequence described in the AD9689 datasheet (Page 81).

The hardware being used is:

• AD9689-2600EBZ Evaluation Board
• ADS8-V1EBZ FPGA Carrier Board

At this stage, I am only checking the JESD PLL lock status and have not connected the JESD lanes to the FPGA yet.

Clock Input : 

A signal generator is connected to the AD9689 CLK+/- inputs.

Configuration Used:

The initialization sequence follows the datasheet example, with the following modifications for 1 GSPS operation:

1. Register 0x056E = 0x10
   • JESD PLL lane-rate range selection
2. Register 0x0590 = 0x0F
   • Subclass 0 operation

All other register writes and the initialization sequence are the same as the datasheet example.

After writing 0x14 to Register 0x0571 (JESD204B Link Power-Up), I wait 5 ms before reading the PLL status register (0x056F).

Issue Observed:

When the ADC sampling clock is 1 GHz, the readback from Register 0x056F is:

0x056F = 0x00

which appears to indicate that the JESD PLL is not locked.

However, when I configure the same hardware using the ACE software, the JESD PLL reports a locked condition.

For verification , I varied the ADC sampling clock frequency and re-ran the complete RTL initialization sequence each time and the readback details for the PLL lock are as follows:

I exported the ACE register configuration and compared it against my RTL configuration. The key JESD-related registers appear to match, but the ACE export contains approximately 577 register writes in total.

My questions are:

1. Is the Page 81 initialization sequence sufficient for Full Bandwidth Mode at 1 GSPS, or are additional registers required beyond the documented sequence?
2. Is Register 0x056E = 0x10 the correct setting for a 1 GSPS configuration with:
   • L = 8
   • M = 2
   • F = 1
   • Subclass 0
3. Does the ACE software perform additional initialization steps that are required for reliable JESD PLL lock?
4. If the full ACE-generated register set must be applied, is there a recommended register programming sequence that should be followed?

Any guidance on  the minimum required initialization sequence for 1 GSPS operation would be appreciated.

Thank you.