Confirmation Request for AD9517 PECL Clock Path Rework on AD9434-FMC-500EBZ

Hi light2445 , 

Thank you for using AD9434. We are looking into your query and will get back to you as soon as possible. 

Regards,

Kim

Thank you. I am also looking forward to a positive outcome.

Hi light2445, 

My understanding base on the schematic that you shared is that you want to bypass the PLL and only use the clock divider of the AD9517. While this configuration might be okay, you need to ensure that your clock source has low jitter.

The User Guide shown in analog wiki website for AD9434 uses PLL as it helps improve the jitter performance of the external clock source.

If you want to proceed with bypassing the PLL, the following modifications should be done.

To answer your questions:

• Capacitor pads 6 & 9 correspond to C209, and pads 7 & 10 correspond to C210. You should remove C209 and C210 as they share the same pads for C304 and C305.
•  C304, uses pads 5 & 6, and C305, uses pads 7 & 8.
• Pads 1 & 2 correspond to C306, and pads 3 & 4 correspond to C307. These should not be populated, along with R311, as they are used for LVDS mode.
• There are no additional components that need to be removed or populate for the AD9517 PECL clock configuration; the setup should work without any issues.
•       

For Reference: EVALUATING THE AD9434 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki]

Warm Regards,

Kim

Hi Kim,

Thank you for your detailed reply and for confirming the required rework.

I have one additional question regarding C311. You listed C311 as one of the components that should be installed for the AD9517 PECL clock configuration, but I would like to understand its function more clearly.

Could you please explain the role of C311 in this configuration?

From the schematic, C311 appears to be part of the AD9517 charge pump / loop filter network, rather than part of the direct PECL output clock path from OUT3 / OUT3_N to the AD9434 CLK+ / CLK− inputs.

Since my intended configuration is to bypass the PLL and use only the AD9517 divider / distribution path, I would like to confirm why C311 is still required.

I have attached two images:
1. A close-up photo of the actual PCB area around C311
2. A cropped schematic image of the charge pump filter section

If C311 must be installed, could you please confirm exactly how it should be connected on the actual PCB?

Based on the schematic, my understanding is that C311 should be installed as a 0.1 uF capacitor across the C311 footprint, between the LF node and the BYPASS_LDO node. However, I would appreciate confirmation using the attached PCB photo, because I want to avoid soldering it to the wrong pads.

Could you please indicate which two pads in the PCB photo correspond to C311?

Thank you again for your help.

Best regards,
light2445

Hi light2445, 

Apologies for confusion. The C311 should not be populated because the clock configuration bypasses the PLL and does not require a charge pump. In addition, the R208 should only be populated with a 100 Ohm resistor for LVPECL configuration (see Figure 73 in the AD9517 data sheet).

Additional board modifications:

• Install jumper cable on P1 pins
• Install R209
• Remove C202 (Optional)
• Either uninstall R213 & R210 or C209 & C210
• Change R206 & R207 to 50 Ohm (Optional) (see AD9517 EVB)
• 

For proper configuration of registers when using an external clock source see AD9517 data sheet.

Warm Regards,

Kim

Hi Kim,

Thank you for the clarification. This helps a lot.

I understand now that C311 should not be populated because my intended configuration bypasses the AD9517 PLL and therefore does not use the charge pump / loop filter.

I also understand that, for the LVPECL configuration, R208 should be populated with 100 ohms, not 200 ohms, based on Figure 73 of the AD9517 data sheet.

I would like to confirm my understanding of the role of R208.

In my configuration, I plan to remove C209 and C210 to disconnect the original direct clock path, and then use the AD9517 OUT3 / OUT3_N LVPECL outputs through C304 and C305 to drive the AD9434 CLK+ / CLK− inputs.

Even after removing C209 and C210, R208 is still required because it acts as the 100 ohm differential termination at the AD9434 clock receiver side. My understanding is that this termination is used to match the differential clock line impedance and reduce reflections / ringing, helping preserve the clock edge quality.

Is this understanding correct?

So my current rework plan is:

already exists

- P1 jumper 
- R209 

Install:
- C302, C303
- C304, C305
- R208 = 100 ohm

Remove:
- C209, C210

Do not populate:
- C311
- C306, C307
- R311

Keep populated:
- R307, R308

Optional:
- Remove C202
- Change R206 and R207 to 50 ohm

Could you please confirm that this is the correct final rework plan for using the onboard Y1 500 MHz oscillator through the AD9517 LVPECL divider path to generate a 250 MHz clock for the AD9434?

Thank you again for your help.

Best regards,
light2445

Hi light2445 ,

Your understanding is correct about the 100 Ohm differential termination.

You may proceed with your final rework plan.

Regards,

Kim

Related Thread: Question about using the on-board Y1 oscillator on the AD9434-FMC-500EBZ with ZedBoard - Q&A - High-Speed ADCs - EngineerZone