Reference Design for AD9689

Hi Sanlayan 

Thanks for your interest in AD9689.

I am not an expert in FPGA design, but as far as I know ADI does not offer a dedicated AD9689 + Kintex UltraScale reference design. The closest and most practical starting point is the AD9208‑DUAL‑EBZ HDL project, since the AD9689 (2.0/2.6 GSPS) is essentially a lower‑rate variant of the AD9208 family (up to 3 GSPS).

I can also only share the source code used with the AD9689 on the ADS7‑V2EBZ, which is based on a Xilinx Virtex‑7 FPGA. This can serve as a useful reference for AD9689.

Additionally, the AD9208 Linux driver page lists AD9689 as one of the supported devices within the same driver family. See AD9208 ADC Linux Driver [Analog Devices Wiki].

For further HDL or GitHub‑related questions, you may create a thread FPGA Reference Designs 

Hi JAlipio ,

Thanks for the information.

As mentioned, please share the source code used with the AD9689 on the ADS7‑V2EBZ.

For the No-OS build for AD9689, can we use the driver in the following project?

https://github.com/analogdevicesinc/no-OS/tree/main/projects/ad9208 

Since AD9689 is not mentioned in the supported device list of the No-OS AD9208 project, could you please confirm whether it is compatible?

Hi Sanlayan 

To proceed with the source code request, kindly accept my friendship request as we need to know some personal information for our verification.

Regarding the No-OS compatibility, you can use the AD9208 No‑OS project as a starting point. If you need additional assistance specifically related to the No‑OS implementation, you may create a thread in Microcontroller no-OS Drivers 

Hi JAlipio ,

Thanks for the reply.

I have accepted your friendship request. Kindly share hdl source code. 

Please let me know process for the verification.

For, No-OS query I will create thread in  Microcontroller no-OS Drivers  

Hi Sanlayan 

I have already sent your request for AD9689. Kindly check your email and verify if you have received the source code. Thank you.

Hi JAlipio 

Thank you.

I have received the source code and i have also installed  Xilinx Vivado 2015.4, as the project was compiled using that version.

Let me go through the source code for the further clarification.

Actually I want to configure the AD9689 SPI interface using RTL code. Could you please provide the recommended SPI register initialization sequence as well the configuration sequence that should be followed for proper configuration?

Hi JAlipio 

Please provide the AD9689 SPI register configuration sequence. 

Hi Sanlayan 

A soft reset can be performed using register 0x00. After the AD9689 is reset, critical registers are automatically loaded with their default values, as listed in the memory map tables (Table 46–53). Please refer to the datasheet for your desired configuration.

Hi JAlipio 

Thanks for the information.

For the set up :AD9689-2000 EBZ evaluation Board.

Can you also confirm, that below mentioned snapshot is the exact sequence that we have to follow after the clock configuration[HMC7044] for the bring up of AD9689 for ADC with DDC option. 

So, If I am using the exact  jesd parameters, there is no need of extra configurations other than mentioned in the snapshot attached right.

Hi JAlipio 

Can you please confirm on the above mentioned queries?