Category: Hardware
Product Number: LTC2123
Hello all
We are using the LTC2123 ADC in a new product. I have the basic functionality of the chip working, but it sometimes gives me bad output data.
To cut to the chase: when the ADC code is near zero, we sometimes (a few per second) get a big glitch in the output as shown below (a plot of ADC outputs). I've done a lot of probing on my board and can't find any corresponding noise or glitch etc. The signals from the driver amps seem OK (no big glitch, common mode looks OK) and the supplies aren't showing any glitches.
I took a number of data captures and put a representative sample below (it doesn't match the above waveform). We see:
- incoming octets have been stacked to make 16b output words
- two 16b output words are output at a time to get our core FPGA clock frequency down
- rx_data[128..143] represent words coming out of one half of the ADC (and 160...191 the other half)
- rx_data[144..159] is typically around 0x8060... and then suddenly it's 0xF058.
- Over many captures the pattern I see is that the ADC is near midscale and the most significant octet seems to get swapped from 0x80 to 0xF0
- I see them from both halves of the LTC2123. I can't see correlation between them
- I have tried another LTC2123 and it does it too
System information:
- 1.8V supply (VDD and OVDD, with separate filtering)
- 250 MHz sample clock
- Internal Vref
- Two-lane mode
- Scrambling off
- Input VCM from my ADC driver amplifiers is OK
- Happens on both channels of the chip, and I haven't seen any correlation between the two halves
- Long Transport Layer Test Pattern is OK
- Modified RPAT Pattern is OK
- I ran the PRBS15 test pattern and compared the outputs of the two lanes for > 40 minutes with no discrepancies. Is there a listing somewhere of what octets should come out of the PRBS15 Pattern?
Can someone help me with this?
