Mitigating Performance Degradation of AD9643 at 499.5 MHz IF Sampling

Hi rexmoon 

Thanks for using AD9643.

1. To improve stability:

• Add narrow band‑limiting around 500 MHz (bandpass sized for your 10–20 MHz BW). This reduces out‑of‑band noise folding and pulse-edge energy that can excite nonlinearity and drift.
• Tune the ADC input RC network at the pins (series damping + small shunt caps / terminations). At 500 MHz you typically need more careful damping to suppress resonances and stabilize impedance.
• For input frequencies at 2nd Nyquist and above, the datasheet highlights that many amplifiers won’t preserve SNR. A transformer or “double balun” coupling with proper RC/termination is often the best approach for SNR/SFDR stability.
• Bottom line: A 500 MHz BPF + properly tuned RC/termination at the ADC pins is the most effective way to improve stability and reduce temperature sensitivity without changing the ADC.

2. Yes, replacing it with a higher-frequency transformer/balun (≥1 GHz) with better amplitude/phase balance at 500 MHz can significantly reduce sensitivity, especially when combined with proper termination/matching at the ADC.

3. The AD9643 has a 1 GHz full‑power input bandwidth and is capable of sampling a 500 MHz IF, performance at this frequency is primarily limited by the external drive network and transformer/balun characteristics rather than the ADC core itself.

Could you also share the following:

• Sample data captures at both 450 MHz and 499.5 MHz (time domain and FFT, if available).
• Front‑end schematic showing the transformer, any matching components, and ADC input connections.

Hello,

The likely cause of the issue that you describe can be attributed to frequency planning where the 3rd harmonic of the ADC and or the driving amplifier before the ADC is falling within the spectrum of the desired signal IF band.   In your specific IF under-sampling case with ADC operating at 117.375 MSPS, the desired IF 20 MHz signal as well as the 3rd harmonic alias back into the center of the 9th Nyquist zone hence making it difficult to digitally filter out the undesired 3rd harmonic during the digital down-conversion and decimation process. 

This concept can be easily seen graphically using an on-line ADI tool  ( https://www.analog.com/en/resources/interactive-design-tools/frequency-folding-tool.html ) .  The first figure generated by an ADI on-line tool shows how a desired single tone (i.e. unmodulated signal) falls next to the 3rd harmonic after aliasing. The second tool shows the spectrum with 20 MHz of  FM modulation on the IF signal where by the power attributed to the 3rd order harmonic is spread over a 60 MHz bandwidth (=3 x 20 MHz) while the 2nd harmonic is spread over 40 MHz (= 2 x 20 MHz).  Note........these tools are not showing effects of intermodulation which is another consideration.

*It is important to note that the effects of HD2  (as well as other even order harmonics) are less of an issue since they alias back to near DC or FS/2.   As a result.........the "balance" of the transformer (or balun) becomes less of an issue albeit the interface circuit (filtering/impedance matching) between balun output and ADC input should be designed to be symmetric (in layout and component values) for 

The optimum solution depends on the type of signal to be demodulated.  If the narrowband IF signal is only FM (or PM) modulated (i.e. FM Chirp Signal)  than intermodulation (IMD3) is less of an issue such that doubling the ADC sample frequency to 234.75 MSPS (=2 x 117.375 MSPS) can place the 3rd harmonic content outside the desired IF band of 20 MHz thus allowing for digital filtering after down-conversion.  The figure shows the effects of doubling the sample rate.

In applications where the desired IF signal is also AM modulated than the 3rd order non-linearity performance is also a consideration.   Reviewing the AD9643 datasheet reveals that its IF performance is quite decent at an IF of 305 MHz with HD3 of 79 dBc suggesting a decent probability of holding 70+ dBc at 499 MHz when designed for a 50 ohm . 

As is often the case...............the single-ended IF amplifier that precedes the balun can be a limiting factor due to its 3rd order output interface performance (OIP3). performance.  To reduce the output power required for the ADC input, one could consider using a higher turns ratio transformer such as pin-compatible TC4-1WA+  (https://www.minicircuits.com/pdfs/TC4-1WA+.pdf  ).    Knowing the input impedance of the ADC, one can optimize the matching network (which also can act as a LPF filter for 3rd+ order harmonics) as shown in AN-225 (https://www.analog.com/en/resources/app-notes/an-2535.html ).  Note that a modified figure is shown below showing balun interface with 3rd order LPF.   Perhaps one of ADI apps engineers can optimize circuit+values such that lowest insertion loss is achieved between balun input and ADC input.

Regards

Thank you for your detailed response. Regarding your comments, I would like to ask for further clarification and share more observations from our tests:

1. Regarding point #3 (1 GHz Full-Power Bandwidth): I have reviewed the AD9643 datasheet, but I could not find a clear reference stating that the Full-Power Bandwidth (FPBW) is 1 GHz. Could you please point out where this is mentioned or how I can verify this? Additionally, could you explain the relationship between FPBW, the amplitude of the IF signal, and the sampling frequency in this context?

2. Observations on Amplitude Stability at 500 MHz: When we sample a 500 MHz IF signal at 117.24 MSPS, we observe that the calculated amplitude level fluctuates slightly over time. Interestingly, this instability is not observed at all when using IF signals below 400 MHz. This specific behavior at 500 MHz is what led us to suspect a potential limitation of the IC or the input network at higher Nyquist zones.

I am preparing the schematic and data captures as you requested and will share them with you shortly.

Best regards,

Hello,

My response is below.

 1) The datasheet specification for FPBW is shown below as well as the equivalent analog input circuit.
Note that the input is "unbuffered" such that the driving source sees the sampling network directly which during the "sampling state" with the CMOS switch being ON consists of the an R-C network (i.e. Ron, Cs) with the FPBW being the -3dB frequency of this RC network.  

That said................this assumes that the driving source has a 0 ohm impedance from DC to infinity which is not possible in the real world.   It is for this reason, that one must perform simulations based on the S-parameters of the AD9643 as well as the entire network (including S-parms of baluns, any filter/matching network with real world R, L and C's, and the driving amplifier).  The application note that I referenced earlier shows how this is done.

2) For debug of your existing design............ideally it would be best to provide an FFT of the data captured by the ADC under the different conditions (i.e. input frequency and sample rate) when providing your circuit with a "filtered" signal from an RF generator that suppresses the harmonics of the RF generator itself.  At the moment.........the theory is that an aliased 3rd harmonic is causing the issue you see (assuming digital filtering removes 2nd harmonic and all other even harmonics).  The FFT captured directly from the ADC (before any digital downconversion/filtering) will reveal the true linearity of your signal chain.  Hopefully you can provide that.

AD_Data_001.zip

Thank you for the detailed explanation regarding the unbuffered input structure and the potential impact of the 3rd harmonic.

As requested, I have attached a ZIP file containing the raw ADC capture data in CSV format. This data represents the 4-channel output under the following conditions:

• Sampling Clock: 117.375 MHz

• RF Input Signal: 499.5 MHz

Hello,

The datasets are two large to process.  I suggest that you keept dataset to 16384 samples where the RF input is a continuous filtered CW tone (as opposed to pulsed) to allow for easier processing.

Also................unless you have software tools to generate FFT, an applications engineer from Analog Devices should be able to generate FFT plots showing measured harmonics, SNR, SINAD ext for the 4 ADC outputs.

Can ADI applications engineer confirm that they will do this??

AD_Data_001_16384.zip

Regarding the dataset, I would like to clarify that the previous data I provided was already captured in CW mode.

As you requested, I have extracted exactly 16,384 samples from that original CW dataset to make it easier for you to process and analyze.

I have a follow-up question regarding the AD9643 datasheet.

The "Features" section states: "IF sampling frequencies of up to 400 MHz." Additionally, the "Theory of Operation" mentions that while operation up to 400 MHz is permitted, it occurs at the expense of increased ADC noise and distortion.

Could you please clarify the following?

1. Does this 400 MHz limit refer to the maximum frequency where the ADC maintains its guaranteed SNR/SFDR performance, or is it a fundamental limitation of the internal sampling network?

2. Given that our application requires sampling at 499.5 MHz, should we consider this 100 MHz gap as the primary reason for the increased temperature sensitivity and amplitude fluctuations we are observing?

3. If the "Full-Power Bandwidth" is indeed 1 GHz as you mentioned, how should we reconcile that with this 400 MHz specification in the datasheet?

I would appreciate your expert interpretation of these specifications.

Best regards,

Hello,

B

Hello,

Plots above are based on importing your 16384 sample data file consisting of 4 channels into TI ADC Pro software for data analysis.   The time domain plots look normal for a CW tone that aliases back very near to FADC/4.   The FFT is more revealing since it reveals very poor SNR performance that is attributed to excessive jitter on the ADC clocking signal.   A zoom FFT (last plot) shows the phase noise consisting of spurs that are at 200 KHz intervals.  A possible cause to this is switching power supply noise used to power up any circuitry associated with external ADC clocking devices as well as possibly the AD9643's AVDD supply (of which internal ADC clocking circuitry is powered). 

This critical supply domain should be powered by a low noise LDO having high PSSR at the frequency regions where a possible Switching supply is used to power the LDO.

From a ADC linearity perspective,  recommend using a filtered CW tone that is perhaps 2 MHz offset from 498.84375 MHz (which results in signal aliasing exactly back to FADC/4).