Category: Datasheet/Specs
Product Number: AD9253
Set a sampling rate of 125 MHz.we can only use the PLL of the XC7A200T FPGA to generate a 125 MHz reference clock for the AD9253.Clock measurement results are shown in the figure. It has been found that with the same interface training program, some boards exhibit significant data errors when measuring external signals after training completion. This is suspected to be a sampling issue with the high-speed LVDS interface. Is it necessary to use a dedicated clock chip as the reference clock?
