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AD9251 "Output Test Mode" results not matching expected digital patterns

Thread Summary

The user is experiencing issues with the AD9251 dual 14-bit ADC where the LSBs (D0/D1) of both channels remain low in all output test modes, despite correct SPI configuration and stable power supply. The final answer suggests verifying the DRVDD voltage level and ensuring the exposed pad is properly soldered to the PCB ground. The user confirmed DRVDD is 3.3V and the exposed pad is well-soldered, but the issue persists. Further tests include checking the jumper settings on the AD9251-80EBZ evaluation board, which are correctly configured.
AI Generated Content
Category: Hardware
Product Number: AD9251

Hello,

We are using AD9251 dual 14-bit ADC and currently validating its "output test modes" as described in AN-877.

However, the digital outputs do not match the patterns described in the documentation.

When selecting test modes such as +FS short, –FS short, checkerboard, and others, the bit patterns on the digital output pins do not align with the patterns defined in AN-877.

Observed behavior:

  • D0A, D1A, D0B, and D1B always remain at logic ‘0’ (verified on DSO), even in modes (+FS short) where these bits should be ‘1’.
  • Whereas digital output pins other than above mentioned are behaving as correctly.
  • Voltage measured across D0A, D1A, D0B and D1B in standalone board is found to be always 0 and Voltage measured across other output pins was up to 2V.

Debugging already performed:

  • SPI write/read verified – registers are correctly configured for output test modes
  • Output mode register (0x14) checked for offset-binary
  • Encode clock present and stable.

Could you please advise what could cause only the LSBs (D0/D1) of both channels to remain low in all test modes, and whether additional configuration or hardware considerations are required for these pins?

Thank you.

Edit Notes

Clarified observed behavior section
[edited by: Devansh at 2:04 PM (GMT -5) on 20 Nov 2025]

Thread Notes

  • Hi  

    Thanks for using AD9251.

    Could you share more details about your setup and configuration, including the schematic and SPI settings? What is your sampling clock rate? Have you confirmed that the power supply is stable?

  • Hi  

    Thank you for your response.

    1.) Setup


    As per the above images, we are using AM64x EVM and custom interconnect board to connect AD9251 eval kit. As per these images the connections are straight forward for both channels and SPI.

    2.) SPI settings:

    We are using 0x0D register to configure "output test modes". Test mode settings and received output is as mentioned in the below Table. 

    Sr. no. Output Test Mode setting Pattern Received Output
    Word 1 Word 2
    1.) 0x02 Positive FS Short 0011 1111 1111 1100 Not applicable
    2.)  0x03 Negative FS Short 0000 0000 0000 0000 Not applicable
    3.)  0x04 Checkerboard 0010 1010 1010 1000 0001 0101 0101 0100
    4.) 0x07 1/0 Word Toggle 0011 1111 1111 1100 0000 0000 0000 0000
    5.) 0x09 1/0 bit toggle 0010 1010 1010 1000 Not applicable
    6.) 0x0A 1x sync 0000 0001 1111 1100 Not applicable
    7.) 0x0B 1 bit high 0000 0000 0000 0000 Not applicable
    8.) 0x0C Mixed-Frequency 0010 0001 1001 1100 Not applicable

    Also verified the value of 0x14(output mode) register, it is 0x00(offset binary output).

    3.) Sampling Clock Rate is 48 MHz

    4.) Yes, the power supply is stable.

  • Hi  

    Voltage measured across D0A, D1A, D0B and D1B in standalone board is found to be always 0 and Voltage measured across other output pins was up to 2V.

    Please confirm the DRVDD voltage level being applied. The voltage measured at the output pins should be approximately 3.25 V when DRVDD = 3.3 V, and around 1.75 V when DRVDD = 1.8 V.

    Additionally, ensure that the exposed pad of the device is properly soldered to the PCB ground. This is critical for effective heat dissipation, noise performance, and mechanical stability.

  • Hi  

    Thank you for your response.

    1) Yes it is confirmed that the DRVDD voltage is 3.3V.

     

    2) The voltage measured at the output pins is not 3.25V but instead the voltage measured at output pins in standalone mode(when only supply and 48 MHz clock is connected) is as attached:

    Sr No Resistor Signal Pin Voltage measured
    1 RN804 D3B 1 1.45
    2 RN804 D2B 2 1.65
    3 RN804 D1B 3 3V3
    4 RN804 D0B 4 0
    5 RN809 D7B 1 0
    6 RN809 D6B 2 3.28
    7 RN809 D5B 3 3.28
    8 RN809 D4B 4 2.95
    9 RN805 D11B 1 0
    10 RN805 D10B 2 0
    11 RN805 D9B 3 0
    12 RN805 D8B 4 0
    13 RN808 D15B 1 3V3
    14 RN808 D14B 2 0
    15 RN808 D13B 3 0
    16 RN808 D12B 4 0
    17 RN801 D0A 1 0
    18 RN801 DCOA 2 1.41
    19 RN801 DCOB 3 1.41
    20 RN801 ORB 4 0
    21 RN806 D4A 1 1.64
    22 RN806 D3A 2 1.64
    23 RN806 D2A 3 1.64
    24 RN806 D1A 4 3V3
    25 RN802 D8A 1 1.64
    26 RN802 D7A 2 1.65
    27 RN802 D6A 3 1.65
    28 RN802 D5A 4 1.65
    29 RN807 D12A 1 1.25
    30 RN807 D11A 2 1.24
    31 RN807 D10A 3 1.2
    32 RN807 D9A 4 1.5
    33 RN803 ORA 1 0
    34 RN803 D15A 2 2.2
    35 RN803 D14A 3 1.46
    36 RN803 D13A 4 1.48

    3) Below are the signals captured for channel A(D0A, D1A, D12A and D13A pins) using DSO(Digital storage oscilloscope). The condition in which this test has been performed is mentioned below :

    • +FS short pattern selected as Output mode test pattern. 

    4) To ensure the exposed pad makes a proper connection, the pads were cleaned with hot air gun to improve the soldering quality.

    We verified the items above and continue to see the issue. Please advise on any further tests or modifications that can be tried.

  • Hi  

    Are you currently using the AD9251-80EBZ evaluation board? If so, have you verified that the jumper settings match those outlined in the Analog Devices Wiki under EVALUATING THE AD9650 / AD9268 / AD9258 / AD9251 / AD9231 / AD9204 / AD9269 / AD9648 / AD9628 / AD9608 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki]?

  • Hi  

    Thank you for your response

    1) Yes, the current board in use is the AD9251-80EBZ evaluation board.

    2) Yes, the jumper settings match those outlined in the Analog Devices Wiki. Since an external clock is being used in the setup, the jumper on J605 is left open, all other jumpers are configured as required.

    However, the expected output is still not observed on the output pins. Additionally, when testing the board in standalone mode with the jumper on J605 connected as recommended and without applying an external clock, the output pins show floating voltages alternating between 0 V and 3.3 V.

    Please advise on any further tests or modifications that can be performed to diagnose or resolve this issue.

  • Hi  

    I wanted to follow up on my last reply to this thread.
    Please let me know if you need any additional information from my side, or if there are any updates regarding this issue. 

    Thank you for your support.