ADC code variations with Power cycle

Hi DataCon 

Thank you for using AD9681.

The AD9681 is optimized for high-speed data conversion, supporting rates up to 125 MSPS, with excellent dynamic performance and low power in space-constrained applications. It provides 14-bit resolution with typical DNL of ±0.8 LSB and INL of ±1.2 LSB, ensuring good linearity and accuracy. However, the device does not include an internal mechanism to guarantee identical code mapping across power cycles without external calibration, and it is not characterized for high precision measurement.

To help minimize variation, please consider the following steps:

• Clock Source Stability: Use a low-jitter, crystal-controlled clock source to maintain stability during power-up and operation.
• Analog Input Configuration: Set the common-mode voltage (VCM) to AVDD/2 for optimal ADC performance.
• Reference Voltage Decoupling: Decouple VREF to ground with a 0.1 µF ceramic capacitor and a 1.0 µF low-ESR capacitor to ensure a stable reference voltage.
• Digital Reset: After the clock is stable, issue a digital reset using Register 0x08 to reinitialize the device correctly and reduce power-cycle variations.
• SPI Configuration: If the issue persists, reconfigure the ADC via SPI after each power cycle to verify all settings are correct and consistent.