Category: Hardware
Product Number: AD9683
Hi,
I have a new design where I am using this ADC (250MSPS version). At the moment I am not able to get "pll locked status" bit in register 0x00A to read "1". I am using the nyquist clock input. Can you confirm that for the 250MSPS version, the clock divider is automatically 2? So I would need to have a 500MHz clock to achieve a 250MSPS sample rate? When I prove the clk+/clk- pins, the input clock seems to be large enough (1V pk to pk, single ended). Are there any other registers that need to be programmed for the pll to lock. I found the following in your kernel driver and I programmed the same thing in the same sequence but still cannot get it to lock.
ret = ad9467_spi_write(spi, 0x5f, (0x16 | 0x1)); // trail bits, ilas normal & pd
ret |= ad9467_spi_write(spi, 0x5e, m << 4 | l); // m=2, l=2
ret |= ad9467_spi_write(spi, 0x66, sel++); // lane id
ret |= ad9467_spi_write(spi, 0x67, sel++); // lane id
ret |= ad9467_spi_write(spi, 0x6e, 0x80 | (l - 1)); // scr, 2-lane
ret |= ad9467_spi_write(spi, 0x70, 0x1f); // no. of frames per multi frame
ret |= ad9467_spi_write(spi, 0x3a, 0x01); // sysref enabled
ret |= ad9467_spi_write(spi, 0x3a, 0x13); // sysref enabled
ret |= ad9467_spi_write(spi, 0x5f, (0x16 | 0x0)); // enable
ret |= ad9467_spi_write(spi, 0x14, 0x00); // offset binary
ret |= ad9467_spi_write(spi, 0x0d, 0x00); // test patterns
ret |= ad9467_spi_write(spi, 0xff, 0x01);
ret |= ad9467_spi_write(spi, 0xff, 0x00);
