Category: Hardware
Product Number: Quad MxFE
I have recently changed the 500 MHz reference oscillator to a cheaper, less stable source. After doing this, issuing the multi-chip synchronization commands fail. Specifically, I am writing value `10` to `multichip_sync`. The driver logs report:
jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition idle -> initialized jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition idle -> initialized jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition initialized -> probed jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition initialized -> probed jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition probed -> idle jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition probed -> idle jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 jesd204: /amba_pl/axi-jesd204-rx@44a90000,jesd204:7,parent=44a90000.axi-jesd204-rx: Possible instantiation for multiple chips; HDL lanes 8, Link[2] lanes 2 jesd204: /amba_pl/axi-jesd204-tx@44b90000,jesd204:8,parent=44b90000.axi-jesd204-tx: Possible instantiation for multiple chips; HDL lanes 16, Link[0] lanes 4 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:2] transition clocks_enable -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: JESD204[0:0] transition clocks_enable -> link_enable axi-jesd204-rx 44a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (WAIT_BS) jesd204: /amba_pl/axi-jesd204-rx@44a90000,jesd204:7,parent=44a90000.axi-jesd204-rx: JESD204[0:2] In link_running got error from cb: -1 jesd204: /amba_pl/spi@44a70000/ad9081@3,jesd204:3,parent=spi0.3: Rolling back from 'link_enable', got error -1
which indicates a failure of the AD9081 JESD FSM completing the LINK ENABLE stage, which is getting caught in the WAIT_BS state (waiting for block synchronization), which appears to be an issue with achieving alignment of the block headers of the multiple JESD links.
The ADF4371 PLL locked status LEDs are lit. The oscillator is a Crystek RFPRO33, outputting 1.67dBm RF power at 500 MHz, which is within the 0-3dBm range listed in the Quad MxFE user guide, and the worst harmonic is -11dB down from the 500 MHz output.
Is this likely to be an issue with the oscillator output? Or are there other issues I may need to address? There were no issues with MCS or JESD links with the previous 500 MHz source, which output 0dBm at 500 MHz. I don't have any data on that sources harmonics.
