AD9680 zeros after decimation

I'm working with AD9680 connected to Artix-7 FPGA through 4 lane JESD. AD clock is 500 MHz, FPGA clock is 125 MHz, subclass 0
All works well on full data rate

But when I set decimation 2 it becomes strange - I've got lot of zeros in output data

I've try set decimation only in 0x201, and with DDC - got slightly visual changes, but zeros in data still present

Here's my decimation setup:

# standby_adc
reg_write_adc 0x003F 0x0
reg_write_adc 0x0040 0x7F
sleep 0.1

# set decimation
case $D in
    1)
    reg_write_adc 0x0200 0x00
    reg_write_adc 0x0201 0x00
  ;;
    2)
    reg_write_adc 0x0200 0x01
    reg_write_adc 0x0201 0x01
    reg_write_adc 0x0310 0x83
    reg_write_adc 0x0311 0x04
    reg_write_adc 0x0314 0x00
    reg_write_adc 0x0315 0x00
    reg_write_adc 0x0320 0x00
    reg_write_adc 0x0321 0x00
  ;;
    4)
    reg_write_adc 0x0201 0x02
  ;;
    8)
    reg_write_adc 0x0201 0x03
  ;;
    16)
    reg_write_adc 0x0201 0x04
  ;;
    *)
    echo "Invalid decimation -$OPTARG" >&2; exit 1 ;;
esac

# JESD power down
reg_write_adc 0x0571 0x15
sleep 0.1

# JESD quick config
log2_f=$(log2 $F)
log2_m=$(log2 $M)
log2_l=$(log2 $L)

# echo $log2_f
# echo $log2_m
# echo $log2_l

val_L=$(((log2_l)<< 6))
val_M=$(((log2_m)<< 3))
val_F=$((log2_f))

val=$((val_L+val_M+val_F))
reg_write_adc 0x0570 $val

# CS = 2, N = 14
val_n=0x80+$N-1
reg_write_adc 0x058F $val_n
# set n' to 16
reg_write_adc 0x0590 0x0F

case $L in
    1)
    reg_write_adc 0x05B0 0xFE
  ;;
    2)
    reg_write_adc 0x05B0 0xFA
  ;;
    4)
    reg_write_adc 0x05B0 0xAA
  ;;
    *)
    echo "Invalid decimation -$OPTARG" >&2; exit 1 ;;
esac

# JESD power up
reg_write_adc 0x0571 0x14

# disable STDBY
reg_write_adc 0x003F 0x80
reg_write_adc 0x0040 0xBF
sleep 0.1

reg_write_adc 0x01 0x02

Am i missing some important config step?