Hello, I'm new to this device, and trying to get it to work.
My setup:
AD6641 connected to PCB, communicating via SPI with my Microzed FPGA board. The ADC is receiving F_CLK=500MHz from ti CDCE62005GZT.
Values of the registers are default, except for 0x14 which is 0x09 (for 2's Comp) and 0x107 which is 0x01, which is dump control via parallel interface. Due to an in interference with another module on my PCB, SDO line is not connected. I have verified that my SPI is working on both reading and writing. DUMP, EMPTY and FULL signs are connected with external lines to the FPGA board.
1. When debugging using the ILA in Vivado, it show that right upon startup, both FULL and EMPTY bits are asserted low. Somehow, I managed to get the FULL bit asserted, but then, while asserting the DUMP signal high, it did not initiate the parallel port interface communication (also checked by the ILA). Unfortunately, I don't have the pictures from the ILA, showing that both the FULL bit high, and the DUMP signal asserted.
2. When I try to apply soft reset by writing 0x38/0x3c/0x1c (I tried all three options) to 0x00, I read all registers afterwards as 0xFF, and need a hard reset inorder to continue.
Any idea on why am I failing to initiate a full data aqcuisition cycle?
Thank you in advance,
Tomer
