Hello,
I am working with the AD9613-250EBZ evaluation board, which is designed for the AD9613 ADC. Using registers 0x16 and 0x17, I adjust the input clock to the FPGA module in order to correctly capture the data.
In test mode, I generated and sampled the ramp and alternating checkerboard patterns. After extracting the data and plotting both channels together in MATLAB (Figures 1 and 2), I noticed the following issues:
1. There is still some noticeable noise on the waveforms, even in test mode. What could be the cause of this noise?
2. The amplitude of waveforms changes periodically every 4096 samples. What might be causing this regular amplitude variation?
3. Figures 3 and 4 are zoomed-in portions of Figures 1 and 2. Upon closer inspection, it appears that the two ADC channels are not exactly aligned — one channel is delayed by exactly one clock cycle relative to the other. This behavior is visible for both test patterns. What could be the reason for this one-clock delay?
Finally, I have a different question:
In my FPGA design, I use the DCO signal as the clock for reading the data. However, on the PCB, the differential DCO pair (DCO_p and DCO_n) is connected to regular I/O bank pins on the FPGA, not to MRCC pins. Could this cause any problems in data capture?
Thank you very much for your help and insights.
figure1:
figure 2:
figure 3:
figure 4:
