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AD9680 Recommended for New Designs
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold...
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AD9680 on Analog.com

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Ask about SYNCINB± pin control register

		
	
				

			

									
					    HDHR1192
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Aug 1, 2025 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user inquired about the AD9680's SYNCINB± pin control at address 0x572 and its application settings. The settings 10 and 11 force the JESD204B link into CGS and ILAS/user data modes, respectively, ignoring the SYNCINB± input. The AD9680 can operate without SYNCINB± if configured to ignore it, particularly in subclass 0 mode. In subclass 1 mode, leaving SYNCINB± unconnected does not affect deterministic latency, but the user should verify the link establishment steps and potential impacts.
                        	    

                
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Product Number:  AD9680  

    		        		    		    

		    		    
		    			

			    
Please tell me about the SYNCINB± pin control at address 0x572.


What applications are the following settings intended for?


10 = ignore SYNCINB± (force CGS)


11 = ignore SYNCINB± (force ILAS/user data)




I thought that the AD9680 could be used without the SYNCINB± being connected (unused), but is that incorrect?

			

			
									
		                             
                        

    

                                            
                 ad9680
                
                                                    
                 Datasheet/Specs
                
                                                    
                 High Speed A/D Converters >10 MSPS
                
                                                    
                 Standard High Speed A/D Converters
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Aug 3, 2025 8:46 PM
            
            
						
			                            
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    Hi  
    

    Thanks for your interest in AD9680.
    

    HDHR1192 said:
    What applications are the following settings intended for?
    

    10 = ignore SYNCINB± (force CGS)
    

    11 = ignore SYNCINB± (force ILAS/user data)
    

    Ignore SYNCINB± (force CGS): This setting forces the JESD204B link into Code Group Synchronization (CGS) mode, regardless of the SYNCINB± input. Useful for debugging or forcing the link to restart CGS without needing an external SYNC signal.
    

    Ignore SYNCINB± (force ILAS/user data): This setting forces the link to proceed to Initial Lane Alignment Sequence (ILAS) or user data phase, again ignoring the SYNCINB± input. Useful for testing or when you want to bypass SYNCINB± control and manually manage link state transitions.
    

    For more details on CGS and ILAS, refer to the JESD204B Link Establishment section in the datasheet.
    

    HDHR1192 said:
    I thought that the AD9680 could be used without the SYNCINB± being connected (unused), but is that incorrect?
    

    Yes, you can operate the AD9680 without connecting SYNCINB±, but only if you configure the device to ignore it using register 0x572. This is especially relevant in subclass 0 mode, where deterministic latency is not required and SYNCINB± is optional.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Aug 5, 2025 2:53 AM
            
            
												
						in reply to JAlipio
					
										
			            		
    
		
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    Hi JAlipio san
    

    Thank you for your response.
    

    I would like to know the precautions when SYNCINB± is left unconnected in subclass 1 mode. Could you please answer the following (1) and (2)?
    

    (1) Steps to establish the link
    I understand that both CGS and ILAS need to be executed in order to establish the link. Is it necessary to control by writing 10 and 11 sequentially to register 0x572? Or is it sufficient to write only 10?
    

    (2) Impact on deterministic latency
    I recognized that SYSREF± and CLK± (device clock) affect deterministic latency in subclass 1 mode, and that SYNCINB± does not have an impact.
    If SYNCINB± is left unconnected (unused) in subclass 1 mode, will it have an impact on deterministic latency?
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Sep 4, 2025 12:31 AM
            
            
												
						in reply to HDHR1192
					
										
			            		
    
		
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    Hi  san
    

    Is there anyone who can answer the above questions?
    

    Regards,
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Sep 16, 2025 1:48 AM
            
            
												
						in reply to HDHR1192
					
										
			            		
    
		
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    Hi  
    

    Please see response below:
    

    (1) JESD204B Link Establishment
    

    Writing 0x572[7:6] = 10 (Force CGS) is sufficient to initiate the JESD204B link when SYNC timing is controlled via SPI. After CGS is forced, the device will automatically proceed to ILAS without needing to write 11 separately. This simplifies the link establishment process. For reference, see JEDEC Standard JESD204B.
    

      

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    FORCE ILAS/User Data (0x572[7:6] = 11) is a diagnostic feature used to isolate JESD204B link issues between the RX and TX. By forcing the link to reinitiate the ILAS, we can observe how each side responds during re-synchronization. This helps determine whether the fault lies in the RX or TX path.
    

    

    

    (2) SYNCINB± in Deterministic Latency
    

    In subclass 1 mode, deterministic latency is primarily influenced by SYSREF± and CLK±. SYNCINB± does not directly affect deterministic latency. If left unconnected, it won’t impact the latency behavior. See JESD204B Survival Guide for more info.
    

      

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    Using SYNCIN signals simplifies system design compared to SPI-based SYNC toggling, especially when synchronizing multiple devices. A single SYNCIN pulse can align multiple JESD204B links, offering better timing control and reducing software overhead by eliminating runtime SPI transactions.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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