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2D2A - ADC/DAC in 6 GSPS Real Mode Full Bandwidth

Category: Software
Product Number: AD9082
Software Version: 1.4
I have a AD9082 chip currently set up in a "4D2A" configuration:
  • 4x DACs: These are working in "complex" mode, processing data at 12 GSPS.
  • 2x ADCs: These are working in "real" mode, processing data at 6 GSPS.
The objective is to change the configuration to "2D2A":
  • 2x DACs: Operate in "real" mode at 12 GSPS, with two DACs active.
  • 2x ADCs: Operate in full bandwidth mode, processing data at 12 GSPS.
This desired configuration is similar to "Example 11" in the AD9082 User Guide (UG-1578).
There isn't a clear example or instructions for setting the DACs to 6 GSPS in real mode while using two DACs at the same time.
Is there any example showing the process/api calls to configure the DACs for this 6 GSPS real mode operation?


Thanks,
Shehzad

Thread Notes

Parents
  • Hi, firstly I want to make few clarifications with the configuration you are trying to make

    • I assume that you are looking for configuration with L=maximum(8), M=2, Interpolation=1x1.  
    • The maximim ADC clock would be limited by the maximum lane rate of 24.75 GHz that can be supported by AD9081. So 6 GHz is the highest clock you can get when NP=16, and ADC clock can be higher than 6 GHz you use NP=12 or 8.
    • You need to choose a mode that support L=8, M=2, and 1x1 decimation from the Table 93 (DAC Path Supported JESD 204C Modes). I see mode 18 (NP=16), 36 (NP=12). If NP=8 is acceptable to you, you can use the mode 19.

    I don't see a ready made example in the API package, but there is an example that matches your target configuration in the following link. 

    https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/quickstart/microblaze

    One of the configuration shown in this page (https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vcu118_ad9082_204c_txmode_18_rxmode_19_lr_24_75Gbps.dts) seems to be close to what you want. You should be able to add a new use case to example API software based on this configuration if that's what you need.

    Hope that helps and let us know if you need further clarification.

    -YH


  • * Yes, L = 8 and M=2 with Interpolation of 1x1
    * I have ADC running at 6GSPS with NP=12 and data rate is 18.5625 GSPS.
    * I have picked mode 36 for DAC and mode 28 for ADC as highlighted in the snippet.

    We have the AD9082 on a custom board so have a different HAL layer and not using the uc_setting.c file instead using the API calls from the software application. Thats why I am more interested in the sequence of the API calls instead of .dts files.

     

  • Hi, I don't think API sequence in the example code that comes with the API release needs to be changer for this particular configuraiton. As I don't see settings similar to your target configuraiton in uc_settings.c, so I provided an example that may help you to add new use case. Could you review the sequency API calls in ad982_app.c in the example code?

  • Do you know where can I get the uc_setting.c  and ad9082_app.c file? Previously I got those from the microzed board petalinux that we bought from ADI. I had these files when I was working on the this chip but then they got misplaced, now I need to change the mode and having difficulty in making sure that what I am doing is correct.

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  • Do you know where can I get the uc_setting.c  and ad9082_app.c file? Previously I got those from the microzed board petalinux that we bought from ADI. I had these files when I was working on the this chip but then they got misplaced, now I need to change the mode and having difficulty in making sure that what I am doing is correct.

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