Defects in ADC data, and timing of 1.8V analog supply & 3.3 V digital supply

Hi mtbeels 

Thanks for using AD9266.

Although the datasheet does not explicitly specify power sequencing requirements, it is generally recommended to bring up AVDD and DRVDD simultaneously.

Additionally, have you tried performing a digital reset by writing 0x03 followed by 0x00 to register 0x08?

Thank you for the reply.  We tried performing a digital reset as you described, and it didn't appear to make a difference.

I suspect something is happening at power-on.  After powering on our electronics, the AD9266 will either produce good data, or garbled data.  But once it is one state, it won't switch to the other until the electronics are completely powered off and back on again.  

We're looking into soldering issues, flux residue, and clock timing, but haven't been able to find the difference between the "good" state and the "bad" state.   

As a test I swapped the ADCs between two boards, one that reliably produced good data, and one that intermittently produced bad data.  The problem followed the ADC.  What are the chances that we have a problem with the ICs?  Is it possible to tell from the markings if they are legitimate parts?  I'm attaching an image of a suspect part.

Hello,

My comments/questions are as follows:
1)  The device name with "-40" indicates that the part is capable of up to 40 MSPS operation while meeting datasheet specification.  Can it be assumed that your application is below or equal to this sample rate?

2) The different speed grades of 20/40/65/80 MSPS is set during factory test where a power bias register is set permanently with higher power settings required to achieve rated performance at higher sample.   The part is branded with the "-X" to designate the speed grade to which the power bias has been set too.  On very rare occasion, we have seen that the wrong branding designator was applied to the device such that a part set for a 20 MSPS setting may be branded with the 40 MSPS or higher settings.   Not saying this is your situation but a simple test (assuming you can easily lower your sample rate) would be to see if the "suspect" part works consistently at 20 MSPS.  If it does.......this would be strong indication that this may be the problem.

3) The fact that the "suspect part" exhibits the same problem on both boards while a "good part" remains performing good in the same socket where the suspect part was soldered indicates the problem is with the part itself.  How many boards have been built and tested to date and how many of these boards with AD9266-40 device exhibit this problem?

Perhaps it is worth discussing with ADI if one (or more) of the suspect devices get returned for to our failure analysis of which they are retested on our ATE (after visual inspection) to see if they perform within our datasheet spec limits.

Note that JAlipio would need to follow up with you on how make Failure Analysis request.

Thank you for the reply, PMH2023.  

We are supplying a 40 MHz clock signal, with the clock divider set to 8, so we are collecting data at 5 MSps.  Would a 20 MSPS device work properly with a 40 MHz clock and clock divider?  Or should we test with a 20 MHz clock instead?

We have approximately 72 boards that came together in the same batch, and roughly 80%-90% have this issue.

Hello JAlipio 

Would you be able to provide more details on how I could request a failure analysis on these ADC parts?  Thank you, mtbeels

Hello,

Your last comment suggesting 80-90% failure rate across 72 boards leads me to believe issue is more of an application issue vs a part issue.  All AD9266 speed grade devices is rated to operate down to 3 MSPS hence all devices should work at 5 MSPS with divided down clock.  My previous comment was under believe that failure rate was very much lower!

Can you confirm that the solder paddle under device is indeed soldered during PCB assembly/soldering phase to a dedicated PCB pad under the device that is attached to AGND?  

Thank you for your reply, I appreciate the input and suggestions.

I removed a problematic device and see evidence of solder on the exposed pad.  I measured resistance between the pad and other AGND locations and see between 3 and 4 ohms.  I resoldered the device and see the same behavior.  

Perhaps it is helpful to summarize the symptoms and what we've tried so far:

• The problematic boards will power on into either a "good" or "bad" state.  Nothing we have tried so far causes the board to switch states after they are powered on.  We've tried heat, cold, and powering off and resetting the AD9266 via software (0x03 followed by 0x00 to register 0x08).  Hard power cycling the unit may cause the board to change states, maybe not.  
• I've noticed that AVDD comes up about 35 ms after DRVDD on the problematic boards, and about 9 ms on the reliable boards.  However, after swapping AD9266 parts between two boards, the problem followed the AD9266.  
• We've had an FPGA engineer review timing of the data read out, and his conclusion is that it is good.  He tested reading back two alternating user codes. 
• The defects we see appear to be digital in nature, the magnitude of the defects correspond with magnitudes of certain bits.  (generally some of the intermediate bits, different from device to device).  The defects are abrupt, from sample to sample.  
• We've used this same board design and BOM for a few years now.  So far, this problem seems to be 100% isolated to one particular batch of boards.

Hello,

Thanks for the additive detail on your last response.  Let's pursue the notion that the issue may be related to power sequencing albeit ADI ADC's are typically designed/tested to be agnostic to supply sequencing issues.

A few comments/questions below:
1)  Is the clock signal present at CLK+/CLK- pins before AVDD is applied or only after this supply is stable?  If not, one should investigate delaying clock until condition is met.

2) In your application, does DRVDD operate from a 3.3 or 1.8 V supply?

3) On problematic boards, have you been able to place probe on both the AVDD and DRVDD supplies to see if the power-up of these response looks normal (i.e. simple ramp with not overshoot and ringing on supply that remains consistent upon power-ups).

4) Assuming if DRVDD is 1.8 V (?)............would it possible to wire in this supply for your AVDD supply?   Perhaps in your power tree to the AVDD supply, you can remove and inductor (or other series component) to isolate the ADC's AVDD supply domain allowing you to easily connect DRVDD supply to AVDD side of the series component pad.

5) If DRVDD is 3.3 V, we would need to get more creative in how we generate an alternative  pull-up AVDD supply from this domain (i.e. two diodes and series resistor 22.5 ohms) that may initially pull-up AVDD supply to around 1 V before the AVDD 1.8 V supply kicks in 10's of msec after.  Note, in this case you will not remove series component but wire in external diodes and series resistor across the DRVDD supply to the AVDD supply.

Thank you again for your very helpful input.  

1) The clock signal appears several seconds (about 5) after AVDD is stable.  Here is one side of the clock signal along with AVDD.  

2) We are using 3.3V for DRVDD.

3) Yes, here AVDD and DRVDD for a good board and problematic board.  First the good board, blue is DRVDD and magenta is AVDD.

Here is a problematic board, same colors:

4&5) Ok, I follow.  I think I can put something together as you suggest to try pulling up AVDD from DRVDD.  Thanks again, I will test this next.  

Hello,

On another option to debug is further is to see whether your power distribution supply network has option of delaying DRVDD by 5+msec relative to AVDD upon AVDD reaching 1.8 V (while accounting for AVDD ramp-up time of around 20 msec).  

Perhaps one can add capacitance to a regulator control pin that increases delay to win it turns on relative to its supply input. 

Note........this could be the solution should we determine if supply sequencing of DRVDD of 3.3 V happens to be the issue.

Regards