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Propagation delay and output valid time for dual port

Category: Datasheet/Specs
Product Number: AD9054A

Hi Team,

If the encode clock pulse is of 200MHz (5ns pulse) to set the conversion rate of 200MSPS then how the valid time and output propagation delay can be met as per the datasheet.

For 100MHz the data valid time is 4.8ns as per the datasheet, what would be the calculation for 200MHz to calculate output valid time.

Regards,

Muhammed Esa 

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  • Hi  

    Thanks for your interest in AD9054A.

    The output data valid time for 100MSPS is based on the maximum output propagation delay (tpd) and the minimum output valid time (tv).

    • Output Data Valid Time = Clock Period - Output Propagation Delay (max) + Output Valid Time (min) = 1/100M - 7.9ns + 2.7ns = 4.8ns

    For 200 MSPS, using the typical values for the AD9054ABST-200.

    • Output Data Valid Time = Clock Period - Output Propagation Delay (typ) + Output Valid Time (typ) = 1/200M - 5.9ns + 5.1ns = 4.2ns
Reply
  • Hi  

    Thanks for your interest in AD9054A.

    The output data valid time for 100MSPS is based on the maximum output propagation delay (tpd) and the minimum output valid time (tv).

    • Output Data Valid Time = Clock Period - Output Propagation Delay (max) + Output Valid Time (min) = 1/100M - 7.9ns + 2.7ns = 4.8ns

    For 200 MSPS, using the typical values for the AD9054ABST-200.

    • Output Data Valid Time = Clock Period - Output Propagation Delay (typ) + Output Valid Time (typ) = 1/200M - 5.9ns + 5.1ns = 4.2ns
Children
  • Hi JAlipio

    Thanks for the response.
    Below is the encode timing for 100MSPS there output valid time is 4.8ns after four pipeline delay and the data is valid for 2.7ns of the 6th encode pulse.

    When i try to draw the encode timing same for 200MSPS, the typical propagation delay is 5.9ns that means after 5 pipeline delay, the data is valid after 6th encode pulse +.9ns , and the data valid time delay is 5.1ns it means the data is valid until the 7th clock, i am still not clear for 200MSPS output valid time calculation


    it would be really helpful if you can give the simplified timing diagram like the above for 100MSPS


    Regards,

    Muhammed Esa 

  • Hi  

    Apologies for the confusion.

    In Dual Port Mode at 200 MSPS, using the typical values for the AD9054ABST-200.

    • Output Data Valid Time = Clock Period (Encode/2) - Output Propagation Delay (typ) + Output Valid Time (typ) = 1/(200M/2) - 5.9ns + 5.1ns = 9.2ns

  • Hi JAlipio,

    Kindly confirm whether my understanding is correct.

    I believe (if we take typical tpd and tv for 200MSPS) each data is seen after 5.9ns of delay from the actual rising edge of the clock (encode) after the 5-clock pipeline delay, in that case the data N is seen at 0.9ns after the rising edge of 7th clock and valid 0.1ns after the rising edge of the 9th clock.

    On Port-A Nth sample is available in 30.9ns (25ns for 5 clock pipeline delay + from 6th clock 5.9ns tpd ) and valid till 40.1ns (considering 9.2ns tv).
    On Port-B N+1 sample is at 35.9ns and valid till 45.1ns.

    Regards,

    Muhammed Esa A

  • Hi  

    Yes, your understanding is correct.