Category: Hardware
Product Number: AD6641
Hello,
I am looking for creative ways for optimizing the high speed FIFO dump readout of the AD6641 using an application processor and without an FPGA.
I am currently focusing on the SPI interface at 25MHz and particularly the streaming capability as described in AN-877. Is there a way to configure the automatic address rollover such that the stream only includes the FIFO dump registers at 0x10A & 0x10B?
If the rollover occurs at the end of the register address map, streaming is only good for reading a single 12bit sample (two register reads) and must be restarted afterwards.
I'm also open for other suggestions...
