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AD9094-1000EBZ: Faulty ACE Plugin and JES204B Link Problem

Category: Hardware
Product Number: AD9094

Hello,

I have recently purchased the AD9094-1000EBZ development board, and have been working through the tutorial posted here:

https://wiki.analog.com/resources/eval/ad9094-1000EBZ

I encountered a problem when opening the ACE software to configure the device. In the tutorial, there is a screen shot of the expected 'Initial Configuration' panel. When I loaded the AD9094 plugin, that panel was greyed out and displayed errors. I could not alter any parameters, and a number of the panel labels differed from the labels in the tutorial. I could read the registers on my AD9094, so I assumed the SPI communication was functional. I could also get the AD9094 to recognize my sampling clock, but configuring the JES204B link was impossible, due to the faulty greyed out 'Initial Configuration' panel.

I contacted the ACE support team, and they explained that the AD9094 plugin version 1.2020.45500 was nonfunctional and released as a mistake. They advised me to delete the plugin, restart the ACE software, and then install and run the AD9694 plugin instead. Now when I run the ACE program with my AD9094-1000EBZ development board and the ADS7-V2 FPGA, the plugin I use Board.AD9094 version 1.2024.43100. I am not sure why the plugin reads 'AD9094' and not 'AD9694', since I deleted the 'AD9094' plugin and am using the 'AD964' plugin, but I was told it doesn't matter.

With the new ACE plugin, I am no longer getting a greyed out 'Initial Configuration' screen. There are functional dropdown menus, and the ACE plugin functions like other ACE plugins I have used before. However, I am still struggling to get the JESD204B link to operate, and now that the new ACE plugin differs from the tutorial, I am unsure what the problem is. The ACE support team informed me that this is outside of their expertise, and that I should contact the product team for the AD9094 here.

I have connected a sampling clock to the ADC (1.2 GHz) (Port J203) and I have connected a REFCLK to the FPGA (600 MHz) (Port J3). I have confirmed that these clock sources are stable, LVDS, and match the parameters in the ACE configuration panels. When I apply the settings in ACE, I get green lights on my AB and CD Clock Detect, and the PLLs for the AB and CD samplers are confirmed. This tells me that my sampling clock is properly received, and that I have SPI communication with the AD9094 board.
However, the JESD204B Link status is down. Again, I have confirmed that my JESD204B configuration expects a 600 MHz REFCLK, and I supply that 600 MHz LVDS clock signal from a reliable source.
I did a bit of searching, and came across this JESD204B tutorial:
In this PDF, it describes the 6 LED status lights on the FPGA that can be used for debugging (page 3). None of those LEDs are active on my FPGA. According to the tutorial, LED1 being off means that the FPGA does not detect my REFCLK.
I have confirmed in my VisualAnalog software that I checked the  'Enable Alternate REFCLK' box in the 'ADC Data Capture Settings -> Device' panel.
I have reconfirmed that my REFCLK matches the JESD204B settings
I have swapped out clock sources for my REFCLK.
I have checked that the 'Lane Control' for the AD9094 device is set to '6.75 Gbps - 13.5 Gbps,' since the lane rate based on my settings is 10xF_adc = 10 x 1.2 GHz = 12 GHz.
The JESD204B tutorial does not give any further guidance in a failed clock detect scenario, other than 'check clock source.'
Is there something wrong with the FPGA programming method via VisualAnalog?
The FPGA image I am using is 'ad9694_ads7v2.bin' and was modified 10/20/2017

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