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Unexpected output of AD9258 ADC in test mode operation

Category: Hardware
Product Number: AD9258

Hi support team,

We developed AD9258 ADC custom board for some project application to capture I and Q sample. we are testing an AD9258 ADC in test mode operation using bare metal code, with test pattern output toggle between 0 and -1. we are capturing output in ILA, we observed that after more iteration of data capturing in ILA random signed bit values like 385, 656, -385 etc. instead of the expected 0 and -1 values. we also changed the DCO (Data Clock Output) delay register setting to adjust the clock delay. but still we are not getting constant 0 and -1 pattern.

please find below screenshot of output data capture in ILA.

Above screenshot shows the 0 and -1 test pattern in AD9258 ADC test mode operation

After multiple time of iteration we are getting random values and sone noisy data as shown in below attached screenshot

 

       

Please provide some solution on that, this is urgent requirement for our project. 

Thanks and regards

 

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  • What Data Output Mode are you using in your design?  Perhaps you can show o'scope picture of the DCO clock signal relative to the data bits using low capacitance, + 1 GHz active probe.  Note...have one probe trigger on the CLK input signal while the high performance active probe is 1st used to measure the DCO signal which is then saved and displayed on the o'scope display.   Once saved.......probe the other data bits to see if they meet the timing specs shown below for the particular mode being used. 
      
    *FYI.......using the same probe for DCO and data bit outputs takes out any possible discrepancy compared to using two different probes that may have slightly different responses/delays.