Unexpected output of AD9258 ADC in test mode operation

Hi ShubhamTupkar 

Thanks for using AD9258.

Could you provide the details of your setup, including the initialization and the schematic if possible. Thank you.

Hi, JAlipio , thanks for response

We developed  AD9258 ADC custom board, we are initializing ADC using SPI protocol. we are using 100MHz reference clock for AD9258. As AD9258 is dual channel ADC, we are using one channel to capture Inphase signal (0 degree) and other channel is use to capture quadrature phase signal (90 degree). 

When  we are testing AD9258 ADC in test mode operation, with test pattern output toggle between 0 and -1, we observed that out of 14 bit, 2 to 3 bits not toggling as it remains continuous high and assuming that may be for that reason we are not getting continuous 0 and -1 pattern in test mode of operation. than we configure DCO output delay register by changing the DCO clock delay output, as attached in below attached image. after setting to DCO clock output delay to 725picosec by setting register value to 09, we are getting 0 and -1 test pattern but observed that after more iteration of data capturing in ILA random signed bit values like 385, 656, -385 etc. instead of the expected 0 and -1 values as attached previously. 

when we are giving input to ADC channel using function generator (sine wave of 500KHz input frequency, 500mvpp amplitude), for same phase i.e. 0 degree to both channel with that setting we are getting sine wave output at ILA window but when we are changing phase (giving different phases as per our project requirements for one channel 0 degree and other channel 5, 10 up to 90 degree) than we observed that ADC output capture at ILA deteriorate, we are not getting sine wave when we are checking ILA capture data in analog form. 

FYI we are using Vref voltage for AD9258 is 1V.

please give some suggestion 

Thank you

Hi ShubhamTupkar 

Are you using an external or internal VREF? Do note that the VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor.

Also, please provide your SPI initialization sequence. Thank you.

Hi

Yes VREF pin is externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR 0.1 μF ceramic capacitor in our custom board hardware.

Please find the below image of SPI initialization sequence that we are using. we are using SPI clock 4MHz.

thank you

What Data Output Mode are you using in your design?  Perhaps you can show o'scope picture of the DCO clock signal relative to the data bits using low capacitance, + 1 GHz active probe.  Note...have one probe trigger on the CLK input signal while the high performance active probe is 1st used to measure the DCO signal which is then saved and displayed on the o'scope display.   Once saved.......probe the other data bits to see if they meet the timing specs shown below for the particular mode being used. 
  
*FYI.......using the same probe for DCO and data bit outputs takes out any possible discrepancy compared to using two different probes that may have slightly different responses/delays.