Problems with sync

Hi CS1998 

Thanks for using AD9653.

Multichip synch functionality is discussed in the Input Clock Divider section on page 26 of the datasheet.

Do also note that if you want to use the sync function, the clock divide in register address 0x0B should not be set to default (0x00).

If you will not use the clock frequency divider and provide the same sample clock for the multiple AD9253, all ADCs will be synchronized even without the SYNC pin.

If you want to use Sync Next Only, 0x109 should be 0x02.

When 0x109 is set to 0x01, clock dividers will be reset to its initial state every time there is a sync pulse.

While if 0x109 = 0x02, resynchronization will happen only on the first sync pulse after the register is written.

Also note that you'll need to satisfy the setup and hold time requirements of the sync pulse with respect to the clock signal, as shown in Table 5 and Table 7 of the datasheet.

If you want to use Sync Next Only, 0x109 should be 0x02.

When 0x109 is set to 0x01, clock dividers will be reset to its initial state every time there is a sync pulse.

While if 0x109 = 0x02, resynchronization will happen only on the first sync pulse after the register is written.

Also note that you'll need to satisfy the setup and hold time requirements of the sync pulse with respect to the clock signal, as shown in Table 5 and Table 7 of the datasheet.

ok, thans