Hello everyone,
I am using the evaluation board AD9083EBZ and trying to implement a subclass 1 JESD204B interface between the ADC and an FPGA.
By default the SYSREF input to the ADC on the eval board is disconnected and the SYSREF+/- pins are tied to about 476mV through a potential divider from AVDD. I want to instead use the on board clock generator AD9528 to generate the SYSREF signal and send it to the 2 devices.
I've managed to configure the SYSREF geneartor and I can output either N-shot pulses or continuous SYSREF from the 2 corresponding outputs (Output 0 going to the FPGA through the FMC connector and Output 12 going to the ADC).
I've confirmed that the SYSREF is being captured on the FPGA side by reading a register flag in the receiving logic IP core. Now I'm trying to do the same for the ADC. As far as I can tell register 0x27E contains the flags that indicate a captured SYSREF and whether the phase is correct (bits 1 and 2 respectively).
Initially I thought that simply installing a jumper across the resistor pads R11 and R12 (on the eval board AD9083EBZ) would enable me to send the SYSREF through and be done with it.
However, after trying multiple SYSREF options the flags in register 0x27E remained 0.
Then I measured the voltage levels going into the SYSREF +/- pins and compared them to the datasheets.
It looks like the voltages match the output levels described in the AD9528 datasheet. I even tried all available options - LVDS (1.25V common mode, ~350mVp-p), LVDS Boost (1.25V common mode, ~550mVp-p) and HSTL (0.95V common mode, ~700mVp-p).
Then I noticed that the SYSREF input to the ADC expects different levels (0.5V common mode, ~700mVp-p typical). In fact, the voltage from the clock gen never dropped below the 0.5V common mode in this configuration.
Since then I've tried different combinations of resistors to bring the common mode voltage to about 0.5V, but that's also resulted in lower p-p amplitude (about 330 - 500mV depending on the output mode).
Right now I'm not sure where the problem is. Some possibilities I'm thinking of:
1. The amplitude is not enough to detect the logic levels at the ADC, even though it's now centered correctly around 500mV. The datasheet doesn't explicitly specify a minimum threshold for detecting 0 or 1 on the SYSREF input, it simply states the typical and max differential peak-to-peak voltage.
2. I'm capturing the SYSREF signal (and perhaps it's supposed to work by simply installing the R11 and R12 jumpers), but register 0x27E is not the correct one to look at for confirmation.
3. There is some configuration that I need to do to the ADC before it will even acknowledge the arrival of a SYSREF pulse (The ADC is configured by calling the functions described in the datasheet with some modifications.
I've verified that the datapath and JTX PLLs are locked by reading the corresponding registers).
Right now it looks like the ADC is sending K characters to the FPGA, by the devices are not synched, so it can't get through the CGS stage. Which is why I'm hoping I can synchronize them using the SYSREF pulse.
I'm looking for any comments that could help me troubleshoot the issue.
Thank you and best wishes,
Tsvetan
