We have a hardware platform containing the AD9683 ADC running at 50 MS/s. It is connected to an AMD ZYNQ-7000 SoC, where i have a running hardware design using the AMD/XILINX JESD204B receiver IP. The hardware design seems to be running correctly (i.e. data-transfer from JESD serial interface to DRAM is working).
Issue(s):
1. ILA configuration data mismatch between AD9683 <=> JESD204 receiver
During the inter-lane-alignment sequence of the JESD-interface the link parameters are transmited to the receiver and stored in a handful of registers that i have read out:
Now compare this to the values as configured in the AD9683's registers:
As you can see all of the parameters match except for:
- Device ID: Is 60 (0x3C) but should be (0xC3)
- JESD204 Version: Is 6 (0b110) but should be (0b001 => this means JESD204B)
- Converter Resolution (N): Is 19 but should be 14
- I also found an error in the AD9683 datasheet: It is stated that the link-parameter CF is equalt to 0 for AD9683, but according to the register description this would be incorrect. The value in the register woud then have to be -1
2. Now for the data coherancy issue:
In order to verify that the transfered data is correct, i have enabled the ADC test-pattern generator.
I tested three options for CS=0 (i.e. no control-bits and tail-bits = 0):
- Checkerboard (the data is constant so no point in showing more than one transfer)
You are looking at a single transfer on the AXI4 bus (32-bit i.e. two samples). As you can see OCTET1 always seems to be correct while OCTET0 contains errors
- Positive Full-Scale
Same again OCTET1 appears to be correct and OCTET0 contains errors, i.e. bits [4:2] are 0 instead of 1
- Negative Full-Scale
Now this is interesting: Both OCTET1 and OCTET0 are correct
But as you will see this is about to change:
I tried the same three patterns but this time for CS=2 (i.e. 2 control-bits and no tail-bits):
- Checkerboard
As before OCTET1 is correct but OCTET0 is false.
- Positive Full-Scale
Now this is interesting: Both OCTET1 and OCTET0 are correct with CS=2
- Negative Full-Scale
What is going on? Now that i set CS=2 OCTET0 reads incorrect at the same locations as it was the case before with CS=0 and positive full scale.
