latency error of LTC2203

Hello,

Best way to confirm that the latency of device is indeed 7 clock cycles is to inject a near full-scale pulse train (pulse-width equal to 1 sample period and period of 10 sample periods or more) into the ADC front-end and monitor the MSB's of the digital output with an oscilloscope as well as the analog input. The transition of MSB bits relative to the analog input pulse would be the pipeline delay.

HI, Sir 

Thank you for your reply, i have done the test as your suggestion, the measured result is the following waveform,

the green  wave is Vin+ and the pink wave is Vin- , the blue wave is input clock

In this test, the Vin+ is always larger than Vin-, so the ADC out  "D15(MSB)"  is always low.

when Vin+ has a large voltage, it makes  D14~D11 of ADC out to be high. 

In this figure, the latency is as show, 4 clock (that is, delay 3 clock)  

Beside, i add 100pF 0603 Capacitor on the input  path of input clock, in the same testing situation the latency become correct. 7

the measured wave form of latency is as the below figure, the figure shows the ADC latency is 7

So, what is going on with this situation? 

Thank you for your help

Hello,

Thanks for doing experiment with adding a capacitor to clock trace resulting in expected latency delay.

Best guess is that the on-chip duty cycle controller based on PLL is misbehaving.  It would appear that this feature is enabled based on your schematic.  Try removing RP128 with jumper installed so that it is disabled so MODE pin is tied to AGND.  Hopefully this will result in expected latency delay without adding the capacitor in the clock line since typically one prefers high slew rate rising/falling edges on clock for best clock jitter performance.

Dear Sir

Thank you for your reply

i will tied MODE pin to AGND, and try later

Beside, according to the datasheet, tied MODE pin to VDD can also disable the clock stabilizer, as the following text in datasheet

and the MODE pin in my schematic is also tied to VDD, but why it seems not really disable if tied to VDD??

Finally, you said that the PLL may be misbehaving, what cause this happened?  And why it may correct when the clock is not a near-perfect square wave?

Sorry i have a lot of questions

Best Regards

ctchan

Hello,

Thanks for showing the table and pointing out that the PLL-based clock stablizer is disabled in your case with MODE tied to VDD.

Upon closer inspection of schematic, it appears that one has option of routing AIN+ or AIN- to the CLK input via JP51.  This is not advisable under any circumstances since the CLK input should be as spectrally clean as possible consisting of the CLK fundamental frequency as well as order harmonics (if perfect square wave).......while noting even order harmonics appear to be any duty-cycle variation from 50%.  Is JP51 removed in your experiments?

Dear Sir,

Thank you for your reply.

I believe the main point is the clean clock source, is that correct?

I am currently testing with a cleaner clock instead of the original one, and it seems to be working fine with a latency of 7.

Best regards,

ctchan

Indeed that is the main point.  Glad to see that problem is now resolved.