Hello,
We have a custom designed PCB for AD6688 connected to an Kintex UltraScale+ FPGA. We have JESD Receiver core running on the FPGA to receive the ADC data.
The ADC is setup with the following configuration:
fs = 3GHz, Real input, only enable ddc0, NCO=1/4fs, Decimation Rate=2, enable HB1 filter and 6dB gain, Complex output, I/Q data rate =1500MSPS
L=8, M=2, F=1, S=2, K=16, N'=16,HD=1
The Receiver IP is setup for a lane rate of 7.5 Gbps.
The input sampling clock of AD6688 is multiplied by 2594, and the reference input clock of 2594 is 100Mhz. The 204B link reference clock of FPGA and ADC is provided by LMK04828, and the frequency is 187.5MHz. They are refer to that same 100MHz clock.
When the normal configuration of this adc is completed and the link between ADC and FPGA is completed, the input port of ADC is tested by spectrometer and it is found that there is 750MHz input spur.
Could you please help me figure out why this spur is observed and how it can be minimised.
Regards.
